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Diffstat (limited to 'src/test/scala/chiselTests/SwitchSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/SwitchSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala index 2cfe16d2..81cf690a 100644 --- a/src/test/scala/chiselTests/SwitchSpec.scala +++ b/src/test/scala/chiselTests/SwitchSpec.scala @@ -12,7 +12,7 @@ class SwitchSpec extends ChiselFlatSpec { elaborate(new Module { val io = IO(new Bundle {}) val state = RegInit(0.U) - val wire = WireInit(0.U) + val wire = WireDefault(0.U) switch (state) { is (wire) { state := 1.U } } |