| Age | Commit message (Expand) | Author |
|---|
| 2015-10-01 | Merge pull request #43 from ucb-bar/new-semantics | Andrew Waterman |
| 2015-10-01 | Change of FIRRTL semantics! | azidar |
| 2015-09-30 | Fixed test so it passes, as it should | azidar |
| 2015-09-30 | Made simple9.fir a short, more isolated test case | azidar |
| 2015-09-30 | Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidth | azidar |
| 2015-09-30 | Fixed naming bug where __1 was matching. Caused lots o issues. | azidar |
| 2015-09-29 | Fixed final bug. All tests pass. Accessors are a go. | azidar |
| 2015-09-29 | Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching... | azidar |
| 2015-08-28 | Moved check type and check kind after check gender | azidar |
| 2015-08-25 | Fixed bug in split expression that leaked connect statements out of a conditi... | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-08-20 | Added tests, cleaned up repo | azidar |
| 2015-08-20 | Added rsh test for const-prop | azidar |
| 2015-08-19 | Added new const propagation test | azidar |
| 2015-08-19 | Fixed width inference bug where constraints were propagating backwards. | azidar |
| 2015-08-18 | Updated shr test so it is an expected pass | azidar |
| 2015-08-18 | Fixed so its length is greater than what it connects to. Changed shr to be e... | azidar |
| 2015-08-17 | Fixed bug where equality between expressions was incorrect, leading to | azidar |
| 2015-08-17 | Added tests for shl and mem. Fixed bug in verilog output of mem size. | azidar |
| 2015-08-04 | Added check for reading from outputs with flips | azidar |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar |
| 2015-08-03 | Fixed performance bug in Split Expressions. Changed delin for connect indexed... | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops strict... | azidar |
| 2015-05-19 | Updated tests | azidar |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates reaso... | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
| 2015-05-13 | Added source indicators from FIRRTL files. Pass in -p i to get them printed. ... | azidar |
| 2015-05-13 | Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug | azidar |
| 2015-05-02 | Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn... | azidar |
| 2015-05-01 | Bug fix. ExpWidth was improperly evaluated during simplify (not subtracting one) | azidar |
| 2015-04-30 | Fixed assignment to outputs not getting emitted from Expand When pass | azidar |
| 2015-04-29 | Fixed bug where a node's width was not equal to its value's | azidar |
| 2015-04-29 | Added dshl and dshr | azidar |
| 2015-04-28 | Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.... | azidar |
| 2015-04-27 | Added on-reset | azidar |
| 2015-04-24 | Merge branch 'master' of github.com:ucb-bar/firrtl into parser | azidar |
