diff options
| author | azidar | 2015-08-03 18:39:55 -0700 |
|---|---|---|
| committer | azidar | 2015-08-03 18:39:55 -0700 |
| commit | ff6dfecf42560ed2e2eb678adc9ca8d868a472bd (patch) | |
| tree | 1483818b3efa226bce74cca560f1aa38102ebcfa /test/passes | |
| parent | ec3bf6a6a74061721024dece229f7a6062f5c7fc (diff) | |
Changed name mangling to use _ as a delin. Fixed bug in checking for
invalid <> assignments.
Diffstat (limited to 'test/passes')
| -rw-r--r-- | test/passes/expand-connect-indexed/bundle-vecs.fir | 10 | ||||
| -rw-r--r-- | test/passes/split-exp/primop.fir | 21 |
2 files changed, 26 insertions, 5 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index e094abcc..70a52088 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -23,11 +23,11 @@ circuit top : ; CHECK: wire b{{[_$]+}}x : UInt<32> ; CHECK: wire b{{[_$]+}}y : UInt<32> ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x - ; CHECK: node i*0 = i - ; CHECK: when eqv(i*0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x - ; CHECK: node i*1 = i - ; CHECK: when eqv(i*1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y - ; CHECK: when eqv(i*1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: node i_1 = i + ; CHECK: when eqv(i_1, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: node i_2 = i + ; CHECK: when eqv(i_2, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: when eqv(i_2, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y j := b.x b.y := UInt(1) diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir new file mode 100644 index 00000000..3b120217 --- /dev/null +++ b/test/passes/split-exp/primop.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Split Expressions +circuit Top : + module Top : + output out : UInt<1> + output out2 : UInt<1> + + wire m : UInt<1>[3] + m[0] := UInt(0) + m[1] := UInt(0) + m[2] := UInt(0) + + wire x : UInt<1> + x := not(UInt(1)) + infer accessor a = m[x] + + out := a + + + |