Added sequential memories. mem no longer exists, must declare either cmem or smem. Added firrtl-gensym utility to generate a hashmap of names

8 files changed, 11 insertions, 11 deletions

diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index cbde1486..eb396bcf 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -3,7 +3,7 @@
 ;CHECK: Expand Accessors
 circuit top :
    module top :
-      mem m : UInt<32>[2][2][2]
+      cmem m : UInt<32>[2][2][2]
       wire i : UInt<4>
       i := UInt(1)
       accessor a = m[i] ;CHECK: accessor a = m[i]
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 718f1d4b..114e5b5b 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -3,7 +3,7 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m : UInt<1>[2]
+      cmem m : UInt<1>[2]
       wire i : UInt<1>
       wire p : UInt<1>
       wire j : UInt<1>
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index 7bee8444..fb537303 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -3,7 +3,7 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m :{ x : UInt<1>, y : UInt<1> }[2] 
+      cmem m :{ x : UInt<1>, y : UInt<1> }[2] 
       wire i : UInt<1>
       wire p : UInt<1>
       wire q : { x : UInt<1>, y : UInt<1> }
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index d42e1dd5..43f61827 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -8,7 +8,7 @@ circuit Stack :
     output dataOut : UInt<32>
     input dataIn : UInt<32>
     
-    mem stack_mem : UInt<32>[16]
+    cmem stack_mem : UInt<32>[16]
     reg sp : UInt<5>
     on-reset sp := UInt<5>(0)
     reg out : UInt<32>
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index bf7635fb..4e0e954c 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -7,7 +7,7 @@ circuit Tbl :
     output o : UInt<16>
     input we : UInt<1>
     
-    mem m : UInt<10>[256]
+    cmem m : UInt<10>[256]
     o := UInt<1>(0)
     when we : 
       accessor T_13 = m[i]
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 875498d6..4d02bcf7 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -9,8 +9,8 @@ circuit Risc :
     input wrAddr : UInt<8>
     input wrData : UInt<32>
     
-    mem file : UInt<32>[256]
-    mem code : UInt<32>[256]
+    cmem file : UInt<32>[256]
+    cmem code : UInt<32>[256]
     reg pc : UInt<8>
     on-reset pc := UInt<8>(0)
     accessor inst = code[pc]
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 29663234..8fe1bc52 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -22,7 +22,7 @@ circuit top :
       ; CHECK: (a$0 a$1 a$2 a$3)[i] := c
       c := j
       
-      mem p : UInt<32>[4]
+      cmem p : UInt<32>[4]
       accessor t = p[i]
       ; CHECK: accessor t = p[i]
       j := t
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index b7915c5d..c39850f4 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -20,9 +20,9 @@ circuit top :
       ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
-      mem m : { x : UInt<32>, y : UInt<32> }[2]
-      ; CHECK: mem m$x : UInt<32>[2]
-      ; CHECK: mem m$y : UInt<32>[2]
+      cmem m : { x : UInt<32>, y : UInt<32> }[2]
+      ; CHECK: cmem m$x : UInt<32>[2]
+      ; CHECK: cmem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
       ; CHECK: accessor c$x = m$x[i]