Updated tests to pipe from stderr to stdout

54 files changed, 54 insertions, 66 deletions

diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index d385fcaa..c219ba17 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Expand Accessors
 circuit top :
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir
index 5cdad6c7..a6b406d1 100644
--- a/test/passes/expand-accessors/accessor-vec.fir
+++ b/test/passes/expand-accessors/accessor-vec.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Expand Accessors
 circuit top :
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index bc1b6892..7fc3a6e5 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Expand Indexed Connects
 circuit top :
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index 7e366400..f7b14c0f 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cd 2>&1 | tee %s.out | FileCheck %s
 ; CHECK: Expand Whens
 circuit top :
    module top :
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index 83f9df6a..ba258857 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ; CHECK: Expand Whens
 circuit top :
    module top :
diff --git a/test/passes/expand-whens/non-ref.fir b/test/passes/expand-whens/non-ref.fir
index 762619a7..32264b9e 100644
--- a/test/passes/expand-whens/non-ref.fir
+++ b/test/passes/expand-whens/non-ref.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Expand Whens
 circuit top :
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 1332395c..c769a4d5 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Expand Whens
 circuit top :
diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
index f752eccd..9b562c90 100644
--- a/test/passes/expand-whens/partial-init.fir
+++ b/test/passes/expand-whens/partial-init.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Expand Whens
 circuit top :
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
index 6d5158cc..f8076a3e 100644
--- a/test/passes/expand-whens/reg-dwc.fir
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 circuit top :
    module top :
       input clk : Clock
diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir
index 3bb9515e..0defc432 100644
--- a/test/passes/expand-whens/reg-dwoc.fir
+++ b/test/passes/expand-whens/reg-dwoc.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 circuit top :
    module top :
       input clk : Clock
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
index bba77902..43136b96 100644
--- a/test/passes/expand-whens/reg-wdc.fir
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ; XFAIL: *
 circuit top :
    module top :
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir
index 954048f2..aac5e278 100644
--- a/test/passes/expand-whens/reg-wdoc.fir
+++ b/test/passes/expand-whens/reg-wdoc.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ; XFAIL: *
 circuit top :
    module top :
diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir
index 4f02896b..b052df5d 100644
--- a/test/passes/expand-whens/scoped-reg.fir
+++ b/test/passes/expand-whens/scoped-reg.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ; XFAIL: *
 circuit top :
    module top :
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index 2203f25e..fafd3dbc 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Expand Whens
 circuit top :
diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir
index 3f88a0d0..b7b6e9fa 100644
--- a/test/passes/expand-whens/wacc-wdc.fir
+++ b/test/passes/expand-whens/wacc-wdc.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ; XFAIL: *
 circuit top :
    module top :
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 118734b7..f3bfa522 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p ct | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p ct 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 0848457b..20f4a340 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p ct | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p ct 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
@@ -39,8 +39,6 @@ circuit top :
       when e :
          x := a
          y := b
-      v := eq(v, UInt(0))
-      ;CHECK: v@<t:UInt> := eq(v@<t:UInt>, UInt("h00000000"))@<t:UInt>
       z := x
    module top :
       input a : UInt<16>
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 8e5afb1b..e12a41af 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p ct | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p ct 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir
index 08396978..47940d25 100644
--- a/test/passes/infer-widths/dsh.fir
+++ b/test/passes/infer-widths/dsh.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cd 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
 
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index efed25ad..a83a79a7 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p ctd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p ctd 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
 circuit top :
@@ -14,7 +14,6 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       output z : UInt<16>
-      output v : UInt<1>
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
       onreset x := UInt(0)
@@ -32,7 +31,6 @@ circuit top :
       when e :
          x := a
          y := b
-      v := eq(v, UInt(0))
       z := x
    module top :
       input a : UInt<16>
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index 1b588c0e..f88afcd6 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cTwd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cTwd 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
 circuit top :
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
index 6227520d..7ef87ec6 100644
--- a/test/passes/inline/gcd.fir
+++ b/test/passes/inline/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Inline Instances
 circuit top :
@@ -14,7 +14,6 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       output z : UInt<16>
-      output v : UInt<1>
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
       onreset x := UInt(0)
@@ -32,7 +31,6 @@ circuit top :
       when e :
          x := a
          y := b
-      v := eq(v, UInt(0))
       z := x
    module top :
       input a : UInt<16>
diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir
index bc803e97..a8dbe4c7 100644
--- a/test/passes/jacktest/ALUTop.fir
+++ b/test/passes/jacktest/ALUTop.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit ALUTop : 
   module ALU : 
diff --git a/test/passes/jacktest/ComplexAssign.fir b/test/passes/jacktest/ComplexAssign.fir
index 8e508d7d..157d96e4 100644
--- a/test/passes/jacktest/ComplexAssign.fir
+++ b/test/passes/jacktest/ComplexAssign.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit ComplexAssign : 
   module ComplexAssign : 
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
index 65efb47f..e19cc0d8 100644
--- a/test/passes/jacktest/Counter.fir
+++ b/test/passes/jacktest/Counter.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit Counter : 
   module Counter : 
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index 4e0387d0..531f71b2 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit EnableShiftRegister : 
   module EnableShiftRegister : 
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index 9baa05a6..f72c994c 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit LFSR16 : 
   module LFSR16 : 
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index ca530ea2..2b965f3d 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit MemorySearch : 
   module MemorySearch : 
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 2fde69f3..5f8d57a8 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit ModuleVec : 
   module PlusOne : 
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 1552e959..0e868d7a 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit Mul : 
   module Mul : 
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index cca645d1..c87f38ac 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit RegisterVecShift : 
   module RegisterVecShift : 
diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir
index 3c70c670..2878f2d9 100644
--- a/test/passes/jacktest/Rom.fir
+++ b/test/passes/jacktest/Rom.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit Rom : 
   module Rom : 
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 5bbec6d2..f3fd331b 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit Stack : 
   module Stack : 
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index b916e0f0..472a2e5a 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit Tbl : 
   module Tbl : 
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
index 0f4bf941..54fe9c48 100644
--- a/test/passes/jacktest/VendingMachine.fir
+++ b/test/passes/jacktest/VendingMachine.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit VendingMachine : 
   module VendingMachine : 
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index f3f12017..6dc9beac 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
 circuit GCD : 
   module GCD : 
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index fda21820..3b58fb81 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 ; CHECK: Done!
 circuit Risc : 
   module Risc : 
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 19b6ac96..c2fbe17e 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cd 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index fb1c8320..1700c4d3 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index 83318e10..19cf7f85 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cd 2>&1 | tee %s.out | FileCheck %s
 
 circuit top :
    module m :
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
index cc8c07e6..c384749f 100644
--- a/test/passes/lower-to-ground/instance.fir
+++ b/test/passes/lower-to-ground/instance.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cdg | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cdg 2>&1 | tee %s.out | FileCheck %s
 
 circuit top :
    module source :
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index fa149ffc..ad5fc4c0 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 63519cac..b896cff4 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
          circuit top :
diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir
index 7e123fc3..a048089b 100644
--- a/test/passes/lower-to-ground/test.fir
+++ b/test/passes/lower-to-ground/test.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cdt | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cdt 2>&1 | tee %s.out | FileCheck %s
 ; CHECK: Done!
 
 circuit Top :
diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 8a86868b..356d494a 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cg 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Resolve Genders
 circuit top :
diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir
index 9ca5d16d..c16949a6 100644
--- a/test/passes/resolve-genders/bigenders.fir
+++ b/test/passes/resolve-genders/bigenders.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Resolve Genders
 circuit top :
diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir
index 1f6b82a5..034c9b48 100644
--- a/test/passes/resolve-genders/bulk.fir
+++ b/test/passes/resolve-genders/bulk.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Resolve Genders
 circuit top :
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index da15cb78..6b2ea41a 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cg 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Resolve Genders
 circuit top :
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
index 993b7cf2..16c4e30b 100644
--- a/test/passes/resolve-genders/ports.fir
+++ b/test/passes/resolve-genders/ports.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cg 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Resolve Genders
 circuit top :
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index 354545fb..1fa046c6 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Lower To Ground
 circuit top :
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index cd02a463..9a335bb9 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p ck | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p ck 2>&1 | tee %s.out | FileCheck %s
 
 ; CHECK: Resolve Kinds
 circuit top :
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index fc49335c..7680f81d 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Split Expressions
 circuit top :
@@ -14,7 +14,6 @@ circuit top :
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
-      output v : UInt<1>
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
       onreset x := UInt(0)
@@ -32,7 +31,6 @@ circuit top :
       when e :
          x := a
          y := b
-      v := eq(v, UInt(0))
       z := x
    module top :
       input clk : Clock
diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir
index 84998989..14c41737 100644
--- a/test/passes/to-flo/gcd.fir
+++ b/test/passes/to-flo/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Flo
 circuit top :
@@ -14,7 +14,6 @@ circuit top :
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
-      output v : UInt<1>
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
       onreset x := UInt(0)
@@ -32,7 +31,6 @@ circuit top :
       when e :
          x := a
          y := b
-      v := eq(v, UInt(0))
       z := x
    module top :
       input a : UInt<16>
diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir
index 9b8732a6..6d1bc819 100644
--- a/test/passes/to-verilog/gcd.fir
+++ b/test/passes/to-verilog/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cw  tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p cw 2>&1 |  tee %s.out | FileCheck %s
 
 ;CHECK: Verilog
 circuit top :
@@ -14,7 +14,6 @@ circuit top :
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
-      output v : UInt<1>
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
       onreset x := UInt(0)
@@ -32,7 +31,6 @@ circuit top :
       when e :
          x := a
          y := b
-      v := eq(v, UInt(0))
       z := x
    module top :
       input a : UInt<16>