sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵	azidar
	roadblock in assigning clocked ports
2016-01-16	New memory works with verilog. Slowly changing tests and fixing bugs.	azidar
	Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-08-24	Changed all tests to use verilog backend.	azidar

2015-07-31	Updated tests to pipe from stderr to stdout	azidar

2015-07-14	Pass most tests. The ones that do not pass are not expected to, yet	azidar

2015-05-18	First pass at a Verilog Backend. Not tested, but compiles and generates ↵	azidar
	reasonable verilog. Requires inlining, future versions will instantiate modules
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be ↵	azidar
	flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-04-28	Instances are now male. Reworked lowering pass to be sane. ↵	azidar
	chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-23	Added new parser. Fixed all Tests. Added on-reset to parser, but don't ↵	azidar
	correctly handle it in compiler.
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar

2015-03-10	Finished resolve genders	azidar