diff options
| author | azidar | 2015-05-18 20:33:23 -0700 |
|---|---|---|
| committer | azidar | 2015-05-18 20:33:23 -0700 |
| commit | 14bb9cda8352388bcd33ba9ca2700805dc51639f (patch) | |
| tree | a9bf8f46948aedadae0fe8e6c423ec48b643786e /test/passes/resolve-genders/accessor.fir | |
| parent | 3336e6beb23e1ba883097eac0c0000269bf8ebfa (diff) | |
First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules
Diffstat (limited to 'test/passes/resolve-genders/accessor.fir')
| -rw-r--r-- | test/passes/resolve-genders/accessor.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir index 31314148..41aea1f4 100644 --- a/test/passes/resolve-genders/accessor.fir +++ b/test/passes/resolve-genders/accessor.fir @@ -3,7 +3,7 @@ ;CHECK: Resolve Genders circuit top : module top : - wire m : UInt<32>[5][5][5] + wire m : UInt<32>[2][2][2] wire i : UInt accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m> accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m> |