New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 17 insertions, 17 deletions

diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 4d816238..64797ece 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -4,31 +4,31 @@
 circuit top :
    module top :
       wire m : UInt<32>[2][2][2]
-      m[0][0][0] := UInt(1)
-      m[1][0][0] := UInt(1)
-      m[0][1][0] := UInt(1)
-      m[1][1][0] := UInt(1)
-      m[0][0][1] := UInt(1)
-      m[1][0][1] := UInt(1)
-      m[0][1][1] := UInt(1)
-      m[1][1][1] := UInt(1)
+      m[0][0][0] <= UInt(1)
+      m[1][0][0] <= UInt(1)
+      m[0][1][0] <= UInt(1)
+      m[1][1][0] <= UInt(1)
+      m[0][0][1] <= UInt(1)
+      m[1][0][1] <= UInt(1)
+      m[0][1][1] <= UInt(1)
+      m[1][1][1] <= UInt(1)
       wire i : UInt
-      i := UInt(1)
+      i <= UInt(1)
       infer accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
       infer accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
       infer accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m>
       wire j : UInt
-      j := c
+      j <= c
 
       infer accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f>
-      x[0][0] := UInt(1)
-      x[1][0] := UInt(1)
-      x[0][1] := UInt(1)
-      x[1][1] := UInt(1)
+      x[0][0] <= UInt(1)
+      x[1][0] <= UInt(1)
+      x[0][1] <= UInt(1)
+      x[1][1] <= UInt(1)
       infer accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f>
-      y[0] := UInt(1)
-      y[1] := UInt(1)
+      y[0] <= UInt(1)
+      y[1] <= UInt(1)
       infer accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f>
-      z := j
+      z <= j
 
 ; CHECK: Finished Resolve Genders