| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
| 2015-04-23 | Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc... | azidar |
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar |
| 2015-04-17 | Fixed bug in primop lowering during type inference. Added reduce instructions... | azidar |
| 2015-04-14 | Finished Split Expressions | azidar |
| 2015-04-14 | Finished inlining pass | azidar |
| 2015-04-13 | Stanza bug | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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