New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 18 insertions, 18 deletions

diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
index 6ae42834..781b949c 100644
--- a/test/passes/inline/gcd.fir
+++ b/test/passes/inline/gcd.fir
@@ -7,7 +7,7 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := subw(x, y)
+      q <= subw(x, y)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -17,22 +17,22 @@ circuit top :
       output z : UInt<16>
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
-      onreset x := UInt(0)
-      onreset y := UInt(42)
+      onreset x <= UInt(0)
+      onreset y <= UInt(42)
       when gt(x, y) :
          inst s of subtracter
-         s.x := x
-         s.y := y
-         x := s.q
+         s.x <= x
+         s.y <= y
+         x <= s.q
       else :
          inst s2 of subtracter
-         s2.x := x
-         s2.y := y
-         y := s2.q
+         s2.x <= x
+         s2.y <= y
+         y <= s2.q
       when e :
-         x := a
-         y := b
-      z := x
+         x <= a
+         y <= b
+      z <= x
    module top :
       input a : UInt<16>
       input b : UInt<16>
@@ -40,11 +40,11 @@ circuit top :
       input reset : UInt<1>
       output z : UInt
       inst i of gcd
-      i.a := a
-      i.b := b
-      i.clk := clk
-      i.reset := reset
-      i.e := UInt(1)
-      z := i.z
+      i.a <= a
+      i.b <= b
+      i.clk <= clk
+      i.reset <= reset
+      i.e <= UInt(1)
+      z <= i.z
 
 ; CHECK: Finished Inline Instances