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authorazidar2015-04-17 10:59:32 -0700
committerazidar2015-04-17 10:59:32 -0700
commit01fa067fe52081463222110b957053734e357f79 (patch)
treee54db5f543c4c9a84e6b120468c4008a4edac8d0 /test/passes/inline
parent06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (diff)
Fixed bug in primop lowering during type inference. Added reduce instructions and renamed concat -> cat, equal -> eq, and added neq and neg
Diffstat (limited to 'test/passes/inline')
-rw-r--r--test/passes/inline/gcd.fir2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
index bf6f87ab..5713cd43 100644
--- a/test/passes/inline/gcd.fir
+++ b/test/passes/inline/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
when e :
x := a
y := b
- v := equal-uu(v, UInt(0))
+ v := eq-uu(v, UInt(0))
z := x
module top :
input a : UInt(16)