diff options
| author | azidar | 2015-07-31 16:05:53 -0700 |
|---|---|---|
| committer | azidar | 2015-07-31 16:05:53 -0700 |
| commit | d5cc3210aabf7b4d69e2f3c5ed45c9c097c3ebdf (patch) | |
| tree | f16aa7305b4ce27d38f679332d7ad37e6f6fef3a /test/passes/inline | |
| parent | 2440b824c68e4604d174e92e26af2c3eca1ec171 (diff) | |
Updated tests to pipe from stderr to stdout
Diffstat (limited to 'test/passes/inline')
| -rw-r--r-- | test/passes/inline/gcd.fir | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir index 6227520d..7ef87ec6 100644 --- a/test/passes/inline/gcd.fir +++ b/test/passes/inline/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Inline Instances circuit top : @@ -14,7 +14,6 @@ circuit top : input clk : Clock input reset : UInt<1> output z : UInt<16> - output v : UInt<1> reg x : UInt,clk,reset reg y : UInt,clk,reset onreset x := UInt(0) @@ -32,7 +31,6 @@ circuit top : when e : x := a y := b - v := eq(v, UInt(0)) z := x module top : input a : UInt<16> |