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2016-08-15Remove stanza (#231)Adam Izraelevitz
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-01-28Updated all tests to passazidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-23Added prefix checker, now compliant with firrtl specazidar
2016-01-17Added check for uint on access index typeazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about ↵azidar
emitting ports (and the assignments to them)
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-10-01Updated tests for previous change that removed RemoveScope test from the ↵azidar
StandardVerilogCompiler
2015-08-26Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.azidar
2015-08-25Fixed bug in split expression that leaked connect statements out of a ↵azidar
conditional assignment
2015-08-25Added width check pass with tests. #22.azidar
2015-08-24Changed all tests to use verilog backend.azidar
2015-08-20Added tests, cleaned up repoazidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-08-04Fixed reading from instance's input ports. Fixed unique naming bug.azidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
invalid <> assignments.
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect ↵azidar
indexed. Fixed various broken tests.
2015-07-31Reading from output ports no longer causes errorsazidar
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Added module name to error messages.azidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-20Added Pad pass to flo.stanza, which pads widths to make := and primops ↵azidar
strict. Have not tested this
2015-05-05Added a bunch of tests. In the middle of implementing check kinds and check ↵azidar
types. Does not compile
2015-05-02Added a infrastructure for check passes, and wrote a fewazidar
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