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authorazidar2015-08-03 11:51:50 -0700
committerazidar2015-08-03 11:51:50 -0700
commit6f098fb5328ebfe3137ff449e9905bdf0f668859 (patch)
tree92c5386f1696920dd9667ffa96f442fce1c44c3c /test/errors
parent342e7760582280d6106a57891d9ea3374551bf77 (diff)
Fixed performance bug in Split Expressions. Changed delin for connect indexed. Fixed various broken tests.
Diffstat (limited to 'test/errors')
-rw-r--r--test/errors/gender/BulkWrong.fir6
1 files changed, 4 insertions, 2 deletions
diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir
index 632dd709..e2dda086 100644
--- a/test/errors/gender/BulkWrong.fir
+++ b/test/errors/gender/BulkWrong.fir
@@ -6,9 +6,11 @@ circuit BTB :
input clk : Clock
input reset : UInt<1>
input req : {valid : UInt<1>, bits : {addr : UInt<39>}}
- output r : UInt<1>
- wire x : {valid : UInt<1>, bits : {addr : UInt<39>}}
+ output r : { x : UInt<1>, flip y : UInt<1>}
+ wire x : {valid : UInt<1>, bits : {addr : UInt<39>}}
req <> x
+
+ wire z : {x : UInt<1>, flip y : UInt<1> }
x.valid := r