diff options
| author | azidar | 2015-07-07 10:13:29 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | d696dd01de8a1a83a376c719490f475be991f387 (patch) | |
| tree | ca5d8f21c0f7787cc6eb00e078f0c0ae1e20a182 /test/errors | |
| parent | 3c8f283b445ca99d4ed4c1e04e2bc8bdcdbd72f6 (diff) | |
Pass most tests. The ones that do not pass are not expected to, yet
Diffstat (limited to 'test/errors')
| -rw-r--r-- | test/errors/high-form/InvalidLOC.fir | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir index cbbb53a9..a4cc49ef 100644 --- a/test/errors/high-form/InvalidLOC.fir +++ b/test/errors/high-form/InvalidLOC.fir @@ -2,15 +2,11 @@ ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. circuit Top : module Top : wire x : UInt add(x,x) := UInt(1) - Register(x,x) := UInt(1) - ReadPort(x,x,x) := UInt(1) UInt(1) := UInt(1) SInt(1) := UInt(1) |