From d696dd01de8a1a83a376c719490f475be991f387 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 7 Jul 2015 10:13:29 -0700
Subject: Pass most tests. The ones that do not pass are not expected to, yet

---
 test/errors/high-form/InvalidLOC.fir | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'test/errors')

diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir
index cbbb53a9..a4cc49ef 100644
--- a/test/errors/high-form/InvalidLOC.fir
+++ b/test/errors/high-form/InvalidLOC.fir
@@ -2,15 +2,11 @@
 ; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
 ; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
 ; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
-; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
-; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
 
 circuit Top :
   module Top :
     wire x : UInt
     add(x,x) := UInt(1)
-    Register(x,x) := UInt(1)
-    ReadPort(x,x,x) := UInt(1)
     UInt(1) := UInt(1)
     SInt(1) := UInt(1)
 
-- 
cgit v1.2.3