Added tests, cleaned up repo

2 files changed, 13 insertions, 1 deletions

diff --git a/test/errors/gender/ReadOutput.fir b/test/errors/gender/ReadOutput.fir
new file mode 100644
index 00000000..14ac75c1
--- /dev/null
+++ b/test/errors/gender/ReadOutput.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Expression out$y is used as a sink but can only be used as a source.
+
+circuit BTB :
+  module BTB : 
+    output out : {x : UInt<1>, flip y : UInt<1>}
+
+    wire w : {x : UInt<1>, flip y : UInt<1>}
+    w.x := UInt(1)
+    w.y := UInt(1)
+    out.x := UInt(1)
+    w <> out
diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir
index b721881e..cb75521a 100644
--- a/test/errors/type/Primop.fir
+++ b/test/errors/type/Primop.fir
@@ -1,7 +1,7 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 ; CHECK: Primop mux requires all operands to have the same type.
 ; CHECK: Primop add cannot operate on non-ground types.
-; CHECK: Primop mux requires argument SInt("h00000001") to be a UInt type.
+; CHECK: Primop mux requires argument SInt("h1") to be a UInt type.
 
 circuit Top : 
   module Top :