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diff --git a/test/errors/gender/ReadOutput.fir b/test/errors/gender/ReadOutput.fir
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+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Expression out$y is used as a sink but can only be used as a source.
+
+circuit BTB :
+ module BTB :
+ output out : {x : UInt<1>, flip y : UInt<1>}
+
+ wire w : {x : UInt<1>, flip y : UInt<1>}
+ w.x := UInt(1)
+ w.y := UInt(1)
+ out.x := UInt(1)
+ w <> out