| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-05-03 | Add test for source locators on multi-line reset registers (#554) | Jack Koenig | |
| Test for #468 | |||
| 2017-04-28 | Add info on reset block lines to ANTLR grammar (#468) | Albert Magyar | |
| Fixes #409 | |||
| 2017-04-20 | move circuit dumping to trace so debug gives annos only (#524) | Colin Schmidt | |
| 2017-04-18 | "Scope" test resource (top.cpp). (#398) | Jim Lawson | |
| Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp. | |||
| 2017-04-13 | Speed up CSE by doing CSE on node expression before recording the node (#543) | Jack Koenig | |
| This means CSE need only be run once to get same QOR and prevents pathological cases. Fixes #448 | |||
| 2017-04-04 | DecorateMems should not delete annoations (#523) | Colin Schmidt | |
| 2017-04-03 | Change implicit value classes to prefix with _ (#522) | Adam Izraelevitz | |
| Fixes bug where arbitrary expressions, if called with .expr, return the same expression. | |||
| 2017-04-03 | Find a single cycle from potentially many in a combinational SCC | Albert Magyar | |
| 2017-03-30 | Make force-append-anno-file work. Fixes #515 (#516) | Jack Koenig | |
| 2017-03-30 | Change findSCCs to iterative implementation (#513) | Albert Magyar | |
| 2017-03-29 | Fix bug where zero width expressions in nodes wouldn't get zeroed (#514) | Jack Koenig | |
| 2017-03-23 | Add pass to detect combinational loops | Albert Magyar | |
| 2017-03-23 | Pass now subclasses Transform (#477) | Adam Izraelevitz | |
| 2017-03-23 | Add TargetDirAnnotation to give transforms access (#503) | Jack Koenig | |
| Also add GlobalCircuitAnnotation for creating similar annotations | |||
| 2017-03-22 | Throw different error message for missing emitanno | Adam Izraelevitz | |
| 2017-03-22 | Fixed zero width perf bug #502 | Adam Izraelevitz | |
| Now remove DefNodes of zero width Don't deeply walk nodes (was the source of the bug) | |||
| 2017-03-22 | Fix unapply of pin | Adam Izraelevitz | |
| 2017-03-22 | Fixing whitespace broke test.... | azidar | |
| 2017-03-22 | Bugfix: apply/unapply of PinAnnotation broken | azidar | |
| 2017-03-17 | Add utilites for digraphs and netlist analyses | Albert Magyar | |
| 2017-03-17 | Give better error message if missing emitedcircuit | Adam Izraelevitz | |
| 2017-03-15 | Use newer rocket regression spec without comb loop | Albert Magyar | |
| 2017-03-14 | Small fix | Adam Izraelevitz | |
| 2017-03-14 | Fixed shadowing of expression lesson2 | Adam Izraelevitz | |
| 2017-03-14 | Style fixes | Adam Izraelevitz | |
| 2017-03-14 | Added lesson2 | Adam Izraelevitz | |
| 2017-03-10 | Changed custom transform option and help text | Adam Izraelevitz | |
| 2017-03-10 | Added comments and section in README | Adam Izraelevitz | |
| 2017-03-10 | Added tutorial pass | Adam Izraelevitz | |
| 2017-03-10 | Added custom transform commandline option | Adam Izraelevitz | |
| 2017-03-10 | Added Circuit mappers | Adam Izraelevitz | |
| 2017-03-09 | make sure infer-rw works for exclusive when statements (#481) | Donggyu | |
| 2017-03-09 | Sint tests and change in serialization (#456) | Adam Izraelevitz | |
| SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+). | |||
| 2017-03-06 | Zero width (#402) | Adam Izraelevitz | |
| * Added Zero width wires. Semantics: - No change to width inference rules, e.g. a<0> + b<2> = c<3> - Replace zero width wires with UInt<1>(0) or SInt<1>(0) - Performs constant prop. - Redo width/type inference * Remove errant println * Moved ZeroWidth after ConvertFixedToSInt * Added more tests, bugfix match on connect Also replaced constprop with infertypes for correctness * Updated to new emitter and test infrastructure | |||
| 2017-03-06 | Fix mistake when rebasing | Adam Izraelevitz | |
| 2017-03-06 | After merge, fixed added transforms | Adam Izraelevitz | |
| 2017-03-06 | Added more stylized debugging style | Adam Izraelevitz | |
| 2017-03-06 | Addresses #459. Rewords transform annotations API. | Adam Izraelevitz | |
| Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it. | |||
| 2017-03-06 | Added pass name to debug logger | Adam Izraelevitz | |
| 2017-03-06 | Add ability to emit 1 file per module (#443) | Jack Koenig | |
| Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated. | |||
| 2017-03-03 | Bugfix: InlineInstances must prefix instances | Adam Izraelevitz | |
| 2017-03-01 | Allow nested digit fields in subfield expressions | Jack Koenig | |
| Workaround for #470. This allows parsing DoubleLits in subfield expressions. | |||
| 2017-03-01 | Fix bug in Lexer rule for DoubleLit and add tests | Jack Koenig | |
| 2017-02-28 | Fix validation print for log-level (#394) | Colin Schmidt | |
| 2017-02-27 | castrhs shouldn't assume rhs is uint (#467) | Angie Wang | |
| * castrhs shouldn't assume rhs is uint * don't cast if types are the same * changed castrhs to catch invalid lhs, rhs type combinations * change error msg | |||
| 2017-02-27 | Add chisel2 isVCSAvailable, isCommandAvailable to FileUtils. (#439) | Jim Lawson | |
| 2017-02-26 | Align types and names of ports in emitted Verilog (#463) | Jack Koenig | |
| 2017-02-23 | move more general utils out of memutils, mov WIR helpers to WIR.scala and ↵ | Angie | |
| update uses | |||
| 2017-02-23 | messed up clocktype match | Angie | |
| 2017-02-23 | fix bug in blackboxsourcehelper apply -- pointed to wrong transform | Angie | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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