diff options
| author | azidar | 2016-12-05 16:31:48 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2017-03-22 10:30:36 -0700 |
| commit | fee603238d73694f3cfa1c3aaa18c5eb43225231 (patch) | |
| tree | 89ec044753f917a141b2057372a277124b49f860 /src | |
| parent | 012b4378f5d8b25c5b19c4c5c5e0e46b9097ce21 (diff) | |
Fixing whitespace broke test....
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/firrtlTests/ClockListTests.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala index 2ac45e0b..20718a71 100644 --- a/src/test/scala/firrtlTests/ClockListTests.scala +++ b/src/test/scala/firrtlTests/ClockListTests.scala @@ -137,7 +137,7 @@ class ClockListTests extends FirrtlFlatSpec { | input clock: Clock |""".stripMargin val check = - """Sourcelist: List(clock, clkC) + """Sourcelist: List(clock, clkC) |Good Origin of clock is clock |Good Origin of c.clock is clkC |""".stripMargin |
