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authorazidar2016-12-05 16:31:48 -0800
committerAdam Izraelevitz2017-03-22 10:30:36 -0700
commitfee603238d73694f3cfa1c3aaa18c5eb43225231 (patch)
tree89ec044753f917a141b2057372a277124b49f860 /src
parent012b4378f5d8b25c5b19c4c5c5e0e46b9097ce21 (diff)
Fixing whitespace broke test....
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/firrtlTests/ClockListTests.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala
index 2ac45e0b..20718a71 100644
--- a/src/test/scala/firrtlTests/ClockListTests.scala
+++ b/src/test/scala/firrtlTests/ClockListTests.scala
@@ -137,7 +137,7 @@ class ClockListTests extends FirrtlFlatSpec {
| input clock: Clock
|""".stripMargin
val check =
- """Sourcelist: List(clock, clkC)
+ """Sourcelist: List(clock, clkC)
|Good Origin of clock is clock
|Good Origin of c.clock is clkC
|""".stripMargin