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authorColin Schmidt2017-04-20 14:40:46 -0700
committerGitHub2017-04-20 14:40:46 -0700
commit10cae2a5dd373056164e2b159d4010ccada156eb (patch)
tree9d9270df60827d18e6da6756000448d7851f6063 /src
parent25a0500dca7e83381739483886c462d7a87721a0 (diff)
move circuit dumping to trace so debug gives annos only (#524)
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Compiler.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index ea801086..6e5cadcd 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -170,7 +170,7 @@ abstract class Transform extends LazyLogging {
remappedAnnotations.foreach { a =>
logger.debug(a.serialize)
}
- logger.debug(s"Circuit:\n${result.circuit.serialize}")
+ logger.trace(s"Circuit:\n${result.circuit.serialize}")
logger.info(s"======== Finished Transform $name ========\n")
CircuitState(result.circuit, result.form, Some(AnnotationMap(remappedAnnotations)), None)