diff options
| author | Adam Izraelevitz | 2017-03-03 18:07:42 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2017-03-22 10:30:36 -0700 |
| commit | 673610d261208aa3c01a21eb0becd2b2a83fe48e (patch) | |
| tree | 56f84b6376f516686aec98704f43230388573275 /src | |
| parent | fee603238d73694f3cfa1c3aaa18c5eb43225231 (diff) | |
Fix unapply of pin
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/wiring/WiringTransform.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala index 5a35d85c..2c122943 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala @@ -87,7 +87,7 @@ class WiringTransform extends Transform with SimpleRun { case (0, 0, p, 0) => state case (s, t, p, c) if (p > 0) & (s == t) & (t == c) => val wis = tops.foldLeft(Seq[WiringInfo]()) { case (seq, (pin, top)) => - seq :+ WiringInfo(sources(pin), comp(pin), sinks("pin:" + pin), pin, top) + seq :+ WiringInfo(sources(pin), comp(pin), sinks(pin), pin, top) } state.copy(circuit = runPasses(state.circuit, passSeq(wis))) case _ => error("Wrong number of sources, tops, or sinks!") |