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2017-05-25Fix performance bug in DCE (#596)Jack Koenig
We walked the whole set of vertices for every dont touch
2017-05-25Fix performance bug in ZeroWidth (#594)Jack Koenig
We were recursing on Types of Expressions which not only is super inefficient (especially since we are already calling InferTypes afterward), but also duplicates each of the Type objects that need changing.
2017-05-19Delete black_box_verilog_files.f if we aren't going to create it - fixes ↵Jim Lawson
#504 (#551)
2017-05-18Upgrade Logging facility (#488)Chick Markley
* Upgrade Logging facility Make thread-safe Make logging by package name work Use caching of class names to level for performance Make some tests to show this working * quick fix for dynamic logging variable * A number of changes based on Adam's suggestions Default LoggerState But there is an invoke method now to handle threading issues. This should be propagated to other projects Driver.execute methods * Add built-in support for string capture of Logging * Usability fixes for logging stuff. Settings made to the logger prior to execute/invoke will be passed along if possible. * A couple style fixes Comment and privatize Logger state * Name and save string buffers used for logging * Fix default logging state setting Fix logging test, did not have change to command argument * comment out logging in InlineInstanceTests * Changed invoke to makeScope Nested makeScopes share same state object Removed earlier named string buffer implementation * Better name for captor get data * Add trace tests to make sure it works too * Fix call into logger settings
2017-05-17Make sure not to DCE input-only extmodules unless specified (#590)Jack Koenig
Fixes #589
2017-05-12Bugfix: renaming instance ports was broken. (#588)Adam Izraelevitz
2017-05-12Fix pad, second try (#465)Adam Izraelevitz
* Bugfix: pad is max(width,const) during constprop * Fixed max syntax
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
Performs DCE by constructing a global dependency graph starting with top-level outputs, external module ports, and simulation constructs as circuit sinks. External modules can optionally be eligible for DCE via the OptimizableExtModuleAnnotation. Dead code is eliminated across module boundaries. Wires, ports, registers, and memories are all eligible for removal. Components marked with a DontTouchAnnotation will be treated as a circuit sink and thus anything that drives such a marked component will NOT be removed. This transform preserves deduplication. All instances of a given DefModule are treated as the same individual module. Thus, while certain instances may have dead code due to the circumstances of their instantiation in their parent module, they will still not be removed. To remove such modules, use the NoDedupAnnotation to prevent deduplication.
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-05-10Fix typo in ExecutionOptionsManager comment (#520)Colin Schmidt
Now you should be able to copy paste the example code :)
2017-05-10Update rename2 (#478)Adam Izraelevitz
* Added pass name to debug logger * Addresses #459. Rewords transform annotations API. Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it. * Added more stylized debugging style * WIP: make pass transform * WIP: All tests pass, need to pull master * Cleaned up PR * Added rename updates to all core transforms * Added more rename tests, and bugfixes * Renaming tracks non-leaf subfields E.g. given: wire x: {a: UInt<1>, b: UInt<1>[2]} Annotating x.b will eventually annotate x_b_0 and x_b_1 * Bugfix instance rename lowering broken * Address review comments * Remove check for seqTransform, UnknownForm too restrictive check
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
Remove infix notation on calls with side effects.
2017-05-03Add test for source locators on multi-line reset registers (#554)Jack Koenig
Test for #468
2017-04-28Add info on reset block lines to ANTLR grammar (#468)Albert Magyar
Fixes #409
2017-04-20move circuit dumping to trace so debug gives annos only (#524)Colin Schmidt
2017-04-18"Scope" test resource (top.cpp). (#398)Jim Lawson
Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.
2017-04-13Speed up CSE by doing CSE on node expression before recording the node (#543)Jack Koenig
This means CSE need only be run once to get same QOR and prevents pathological cases. Fixes #448
2017-04-04DecorateMems should not delete annoations (#523)Colin Schmidt
2017-04-03Change implicit value classes to prefix with _ (#522)Adam Izraelevitz
Fixes bug where arbitrary expressions, if called with .expr, return the same expression.
2017-04-03Find a single cycle from potentially many in a combinational SCCAlbert Magyar
2017-03-30Make force-append-anno-file work. Fixes #515 (#516)Jack Koenig
2017-03-30Change findSCCs to iterative implementation (#513)Albert Magyar
2017-03-29Fix bug where zero width expressions in nodes wouldn't get zeroed (#514)Jack Koenig
2017-03-23Add pass to detect combinational loopsAlbert Magyar
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-23Add TargetDirAnnotation to give transforms access (#503)Jack Koenig
Also add GlobalCircuitAnnotation for creating similar annotations
2017-03-22Throw different error message for missing emitannoAdam Izraelevitz
2017-03-22Fixed zero width perf bug #502Adam Izraelevitz
Now remove DefNodes of zero width Don't deeply walk nodes (was the source of the bug)
2017-03-22Fix unapply of pinAdam Izraelevitz
2017-03-22Fixing whitespace broke test....azidar
2017-03-22Bugfix: apply/unapply of PinAnnotation brokenazidar
2017-03-17Add utilites for digraphs and netlist analysesAlbert Magyar
2017-03-17Give better error message if missing emitedcircuitAdam Izraelevitz
2017-03-15Use newer rocket regression spec without comb loopAlbert Magyar
2017-03-14Small fixAdam Izraelevitz
2017-03-14Fixed shadowing of expression lesson2Adam Izraelevitz
2017-03-14Style fixesAdam Izraelevitz
2017-03-14Added lesson2Adam Izraelevitz
2017-03-10Changed custom transform option and help textAdam Izraelevitz
2017-03-10Added comments and section in READMEAdam Izraelevitz
2017-03-10Added tutorial passAdam Izraelevitz
2017-03-10Added custom transform commandline optionAdam Izraelevitz
2017-03-10Added Circuit mappersAdam Izraelevitz
2017-03-09make sure infer-rw works for exclusive when statements (#481)Donggyu
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2017-03-06Zero width (#402)Adam Izraelevitz
* Added Zero width wires. Semantics: - No change to width inference rules, e.g. a<0> + b<2> = c<3> - Replace zero width wires with UInt<1>(0) or SInt<1>(0) - Performs constant prop. - Redo width/type inference * Remove errant println * Moved ZeroWidth after ConvertFixedToSInt * Added more tests, bugfix match on connect Also replaced constprop with infertypes for correctness * Updated to new emitter and test infrastructure
2017-03-06Fix mistake when rebasingAdam Izraelevitz
2017-03-06After merge, fixed added transformsAdam Izraelevitz
2017-03-06Added more stylized debugging styleAdam Izraelevitz
2017-03-06Addresses #459. Rewords transform annotations API.Adam Izraelevitz
Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it.