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AgeCommit message (Expand)Author
2018-07-26Support for load memory annotations in chisel (#833)Chick Markley
2018-07-20Constant prop add (#849)albertchen-sifive
2018-07-11Make InstanceGraph have deterministic and use defined iteration order (#843)Jack Koenig
2018-07-10Fix bug in zero-width renaming (#845)Jack Koenig
2018-07-10Combinational Dependency Annotation (#809)Adam Izraelevitz
2018-07-03Improve code generation for smem wmode and [w]mask ports (#834)Andrew Waterman
2018-07-02Make ZeroWidth properly rename removed empty aggregates (#839)Jack Koenig
2018-06-28Make CheckCombLoops find combinational nodes with self-edges (#837)Albert Magyar
2018-06-28Protobuf (#832)Jack Koenig
2018-06-21--infer-rw should take no argument (#829)Schuyler Eldridge
2018-06-14Fix TopWiringTests use of /tmp. (#825)Jim Lawson
2018-06-13Resolve register clock dependencies in RemoveWires (#823)Schuyler Eldridge
2018-06-11Allow escaped single quotes in RawParams (#820)Richard Lin
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
2018-06-06Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794)Chick Markley
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
2018-05-30Makes ExpandWhens preserve connect Infoschick
2018-05-29Fix pad (#817)Jack Koenig
2018-05-23Add Circuit as option to FirrtlOptions (#814)Jack Koenig
2018-05-21Fix more problems with zero width things. (#779)grebe
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
2018-05-11TopWiring Transform (#798)alonamid
2018-05-09Bugfix: ports of a temporary name would break const-prop (#806)Adam Izraelevitz
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
2018-04-11Cleaning up BlackBoxSourceHelper (#786)Henry Cook
2018-04-11Make DiGraph.linearize be iterative instead of recursive (#785)Jack Koenig
2018-04-10Fix bug in Constant Propagation for registers propped to zero (#787)Jack Koenig
2018-04-03Make Dedup properly dedup ExtModules (#781)Jack Koenig
2018-04-02CyclicException identifies a problem node. (#778)Chick Markley
2018-03-28Enhance RenameMap to support circuit renaming (#775)Jack Koenig
2018-03-28Replace unconnected registers with 0 in Constant Propagation (#776)Jack Koenig
2018-03-27Const prop improvement (#772)Jack Koenig
2018-03-23Make Register Update Flattening a Transform and Delete Dangling Nodes (#692)Jack Koenig
2018-03-22Better bad annotation file error reporting (#771)Jack Koenig
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
2018-03-21Add SyntaxErrorsException as a type of ParserException (#770)Jack Koenig
2018-03-19Pass up annotations in return value from Driver.execute (#760)Chick Markley
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
2018-03-02Fix annotation deserialization of component subfields (#750)Jack Koenig
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-26Rename loadAnnotations -> getAnnotations (#747)Jack Koenig
2018-02-23Add graph summation "+" to DiGraph (#744)Schuyler Eldridge
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-21Change primop arg type (#587)Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
2018-02-08CheckHighForm should check that Bits MSB >= LSB (#738)Schuyler Eldridge
2018-02-07Fix EulerTour for circuits with one module (#736)Schuyler Eldridge
2018-01-30Make Constant Propagation respect dontTouch on registersJack Koenig
2018-01-30Fix bug incorrectly propagating constants on submodule inputsJack Koenig
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
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