Resolve register clock dependencies in RemoveWires (#823)

Candidate fix for #749
This adds DefRegister netlist ordering to RemoveWires

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
index cfc03ad9..f162f32c 100644
--- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -40,6 +40,24 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
     (nodes, wires)
   }
 
+  def orderedNames(circuit: Circuit): Seq[String] = {
+    require(circuit.modules.size == 1)
+    val names = mutable.ArrayBuffer.empty[String]
+    def onStmt(stmt: Statement): Statement = {
+      stmt map onStmt match {
+        case reg: DefRegister => names += reg.name
+        case wire: DefWire => names += wire.name
+        case node: DefNode => names += node.name
+        case _ =>
+      }
+      stmt
+    }
+    circuit.modules.head match {
+      case Module(_,_,_, body) => onStmt(body)
+    }
+    names
+  }
+
   "Remove Wires" should "turn wires and their single connect into nodes" in {
     val result = compileBody(s"""
       |input a : UInt<8>
@@ -120,4 +138,16 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
           "node y = not(b)")
     )
   }
+
+  it should "work for multiple clocks" in {
+    val result = compileBody(
+      s"""|input clock: Clock
+          |reg a : UInt<1>, clock
+          |node clock2 = asClock(a)
+          |reg b : UInt<1>, clock2
+          |""".stripMargin
+    )
+    val names = orderedNames(result.circuit)
+    names should be (Seq("a", "clock2", "b"))
+  }
 }