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AgeCommit message (Expand)Author
2018-08-03add link to repo for firrtl syntax highlighting in sublime text 3kritik bhimani
2018-08-03Fix Travis (#858)Jack Koenig
2018-07-26Support for load memory annotations in chisel (#833)Chick Markley
2018-07-20Constant prop add (#849)albertchen-sifive
2018-07-11Make InstanceGraph have deterministic and use defined iteration order (#843)Jack Koenig
2018-07-10Fix bug in zero-width renaming (#845)Jack Koenig
2018-07-10Combinational Dependency Annotation (#809)Adam Izraelevitz
2018-07-10InferWidths: improve performance (#846)edwardcwang
2018-07-07Missing match on PassExceptions fixed. (#844)Chick Markley
2018-07-03Improve code generation for smem wmode and [w]mask ports (#834)Andrew Waterman
2018-07-02Make ZeroWidth properly rename removed empty aggregates (#839)Jack Koenig
2018-06-28Make CheckCombLoops find combinational nodes with self-edges (#837)Albert Magyar
2018-06-28Protobuf (#832)Jack Koenig
2018-06-22Remove checkboxes from issue/pr templatesedwardcwang
2018-06-21Provide a ProcessLogger() ot capture all output in isCommandAvailable(). (#831)Jim Lawson
2018-06-21--infer-rw should take no argument (#829)Schuyler Eldridge
2018-06-18Bump ANTLR version and change directory to play nice with IntelliJ (#824)Jack Koenig
2018-06-15Improve Parser and Visitor (#819)Jack Koenig
2018-06-14Fix TopWiringTests use of /tmp. (#825)Jim Lawson
2018-06-13Resolve register clock dependencies in RemoveWires (#823)Schuyler Eldridge
2018-06-12Deprecate SingleStringAnnotation (#811)Jack Koenig
2018-06-11Allow escaped single quotes in RawParams (#820)Richard Lin
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
2018-06-11Use attach to connect analogs when grouping (#805)Colin Schmidt
2018-06-11Fix some typos in leftovers.txt (#822)Felix Yan
2018-06-10ucb-bar -> freechipsproject in clone instructionLeonard (Lenny) Truong
2018-06-08Add a blacklist option for paths (#810)Colin Schmidt
2018-06-06Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794)Chick Markley
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
2018-05-30Merge pull request #816 from freechipsproject/expand-when-preserve-info-1Jack Koenig
2018-05-30Improve Travis configuration and revert Yosys versionJack Koenig
2018-05-30Makes ExpandWhens preserve connect Infoschick
2018-05-29Fix pad (#817)Jack Koenig
2018-05-23Add Circuit as option to FirrtlOptions (#814)Jack Koenig
2018-05-21Fix more problems with zero width things. (#779)grebe
2018-05-17Change from Yosys 0.7 to master (#812)Jack Koenig
2018-05-16Bump version of Verilator used in Travis to 3.922 (#784)Jack Koenig
2018-05-15Don't use bash to determine command availability - fixes #807 (#808)Jim Lawson
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
2018-05-11TopWiring Transform (#798)alonamid
2018-05-09Bugfix: ports of a temporary name would break const-prop (#806)Adam Izraelevitz
2018-05-02Deprecate old WiringUtils methods/classes (#801)Schuyler Eldridge
2018-04-29Fix pathological behavior of Namespace for name collisions (#788)Jack Koenig
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
2018-04-16Cleaning up BlackBoxSourceHelper - use absolute file paths. (#789)Jim Lawson
2018-04-13Remove infinitely recursive function (#790)Jack Koenig
2018-04-11Cleaning up BlackBoxSourceHelper (#786)Henry Cook
2018-04-11Make DiGraph.linearize be iterative instead of recursive (#785)Jack Koenig
2018-04-10Fix bug in Constant Propagation for registers propped to zero (#787)Jack Koenig
2018-04-03Make Dedup properly dedup ExtModules (#781)Jack Koenig
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