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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This changes the CheckTypes.UniferredWidth exception to include the pretty
printed Target that was uninferred and suggests to the user that they may
have forgotten to assign to it. This changes the CheckTypes pass to
communicate the necessary Target information during AST traversal such
that when an uninferred width is found, the Target is known and available.
This also adds one test checking the message of the UniferredWidth
exception.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds a pretty printer for firrtl.annotation.Target and associated
tests. This uses a tree-like output where the following target
~Circuit|Module/foo:Foo>ref.field[0] will serialize to:
circuit Circuit:
└── module Module:
└── foo of Foo:
└── ref.field[0]
This enables better error messages and a human readable syntax better than
the existing serialize method (and avoiding the need for users to
understand the Target serialization syntax), but that is not intended to
be deserialized nor space efficient.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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It is O(n) and every use is in an O(n) iteration resulting in O(n^2).
Same information can be extracted from create_exps which happens to also
be called at every use of get_flip.
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When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917
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Formerly #865
Major Code Changes/Features Added:
Added Target trait as replacement for Named
Added TargetToken as token in building Target
Added GenericTarget as a catch-all Target
Added CircuitTarget, ModuleTarget, ReferenceTarget, and InstanceTarget
Added ResolvePaths annotation
Added EliminateTargetPaths (and helper class DuplicationHelper)
Updated Dedup to work with instance annotations
Updated RenameMap to work with instance annotations
DCE & ConstantProp extend ResolveAnnotationPaths
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This reverts commit 7e2f787e125227dc389d5cf1d09717748ecfed2e.
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Added Target, which now supports Instance Annotations. See #865 for details.
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This wraps interactions with a BlackBox resource file such that a
FileNotFoundException are wrapped in a BlackBoxNotFoundException and
rethrown. This provides a better, verbose error message to the user and avoids a
FileNotFoundException showing up as an internal FIRRTL error.
This adds tests that the expected exception is thrown for both
BlackBoxResourceAnno and BlackBoxResourceAnno.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This moves VerilogRename out of Passes.scala and genericizes it as the new
Transform KemoveKeywordCollisions. This new Transform will remove keywords
for arbitrary sets of reserved keyword.
This adds VerilogRename back as a class instead of an object.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Summary of changes to firrtl.passes.VerilogRename:
- Use "_" to mangle names that conflict with Verilog
keywords (previously "$")
- Rewrite to operate on the whole AST to propogate mangled ports and
module names
- Make VerilogRename a Transform (was previously a Pass)
- Renames are now propagated
- Adds documentation for new VerilogRename
This makes the VerilogRename Transform (previously a Pass) use an
underscore ('_') instead of a dollar sign ('$') to mangle names that
conflict with Verilog keywords. This prevents problems with potentially
buggy tools that are not expecting '$' in Verilog names.
This reimplements VerilogRename to be safe for name collisions that may
occur anywhere in the AST, e.g., in ports, module names, circuit names, or
in any statements/expressions. Previously, names were only mangled in
statements and in place. This resulted in problems where renames of ports
in a child's namespace would not be guaranteed to be mangled the same way
in a parent's namespace. The algorithm is reimplemented to walk all
modules in reverse topological order (from leafs to main) and relying on a
RenameMap to track name changes.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Summary of changes:
- Use "_" as an inlining delimiter instead of "$"
- Makes inlining avoid namespace conflicts
This changes the delimiter used for inlining to "_" instead of "$". This
avoids problems with buggy parsers that may not handle "$" correctly. As
ClockListTransform relies on the explicit use of "$", the delimiter is a
FIRRTL-private val that the ClockListTransform overrides (to the original
"$").
Namespace conflicts could occur previously, but are very rare as users
will almost never use "$" in a name (even though it's allowed by both the
FIRRTL and Verilog specifications). Moving to "_" increases the
probability of namespace conflicts occurring. This adds explicit checking
that inlined names will not introduce namespace conflicts and that
generated names are prefix unique (as defined in the spec).
Note: inlined modules may not have unique prefixes. A test is included
that this is the case and an ignored test shows what prefix uniqueness
would look like.
MISC:
- [skip chisel tests]: Changing the delimiter causes the Chisel
InlineSpec to fail as this explicitly checks for "$".
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds a utility, expandPrefixes, that expands a string into all
possible prefixes based on a delimiter. Any repeated occurrence of the
delimiter is viewed as a contributing to a prefix. E.g., "foo_bar" expands
to Seq("foo_", "foo_bar"). This is useful for inlining and keyword
mangling on LowForm. You would like to be able to generate a new name that
is prefix unique with respect to a namespace.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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When different levels of the circuit were annotated, the TopWiring signals of the lower levels would "run-over" the TopWiring signals of the higher levels
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* bug fixes in TopWiring
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add description nodes, transform; modify VerilogEmitter to emit comments
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Previously, mems marked no dedup would prevent mems with the same
instance name in other modules from deduping
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Fixes #780
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Fixes a bug where registers could be instantiated after nodes that
referred to them
Also add WRef.apply utility for nodes
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* Support for load memory annotations in chisel
This PR
* Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler
* remove from VerilogCompiler
* move to VerilogEmitter
* Changes the verilog emitter to allow programmatic access to the verilog module declaration
* Creating a bindable module requires headers to match
* Provides a unit test that shows how to generate a bindable module.
* Binding support
Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading
* Binding support
- Fixed bug that handled suffixes on memory initializing files
* Binding support
- Add a bit more doc to the API provided by the VerilogRenderer
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* add FoldADD to const prop, add yosys miter tests
* add option for verilog compiler without optimizations
* rename FoldLogicalOp to FoldCommutativeOp
* add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation
* add constant propagation for Tail DoPrims
* add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim
* add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
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Previously, Vecs of Bundles that contained a zero-width element would
result in a ClassCastException
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[skip formal checks] LEC passes with Formality
* Improve code generation for smem RW-port wmode port
A common case for these port-enables is
wen = valid & write
ren = valid & !write
which the RW-port transform currently turns into
en = (valid & write) | (valid & !write)
wmode = valid & write
because it proved `wen` and `ren` are mutually exclusive via `write`.
Synthesis tools can trivially optimize `en` to `valid`, so that's not a
problem, but the wmode field can't be optimized if going into a black box.
This PR instead sets `wmode` to whatever node was used to prove
mutual exclusion, which is always a simpler expression. In this case:
en = (valid & write) | (valid & !write)
wmode = write
* In RemoveCHIRRTL, infer mask relative to port definition
Previously, it was inferred relative to the memory definition causing
the mask condition to be redundantly conjoined with the enable signal.
Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to
improve QoR.
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Fixes #756
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Add support for ProtoBuf serialization and deserialization
* Add support for additional features in .proto description
Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params
* Add support for .pb input files
This involves an API change where FIRRTL no longer implicitly adds .fir
to input file names
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This fixes --infer-rw to not expect an argument. After the annotations
refactor, no option was required, but some legacy code remained.
This also updates the test cases to be more correct and not specify an
option to --infer-rw.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Relying on /tmp as a place for test output will fail on multiuser systems and may fail if multiple instances of tests are running for the same user.
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Candidate fix for #749
This adds DefRegister netlist ordering to RemoveWires
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Escape raw params using \'
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Also minor cleanup to literal construction in Visitor
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Add optional argument to verilogToCpp to suppress VCD
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This enables the pattern of attaching "through" a wire to give better
Verilog that also works in Verilator
Use WrappedExpression when combining attaches in ExpandWhens
to ensure no duplication of references in resulting, combined attaches
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* Collects Infos found for symbols
* Merges multiple sources for symbol into MultiInfo
* Restores these Infos on connect statements.
* Add test showing preserved Infos
* Changed ++ methods on the Info sub-classes
* Ignore NoInfo being added
* Fixed way adding was implemented in MultiInfo
* Made InfoMap a class which defines the default value function
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* Make VerilogEmitter properly handle pad of width <= width of arg
* Constant prop pads with pad amount <= width of arg
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This should close #757. It should also allow for stop() and printf()
to be used with zero-width fields.
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Replaces old VerilogWrap which didn't work with split expressions and was
actually buggy anyway. This functionality reduces unnecessary intermediates in
emitted Verilog.
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* top wiring transform
* fixup comments
* TopWiring cosmetics
* move prefix into TopWiringAnnotation
* remove test function from transform file
* add ChildrenMap to InstanceGraph API
* use namespaces
* remove wiringUtils from TopWiring pass
* enable multiple output functions
* TopWiring cosmetics, tests and lowform
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* Change VerilogMemDelays to put new Statements at end of Module
Fixes #547
This is instead of putting them right after the modified DefMemory which could
result in use before declaration errors for things that feed into the new
logic.
* Adds tests that show VerilogMemDelays crashing. (#792)
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Create sources once per module, not once per instance
Clean up writing the file list
Don't prepend file list with '-v's (non-standard and not all verilog)
Change file list file name (not all verilog)
Use ListSets for determinism
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Also make DiGraphTests more ScalaTest-y
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