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AgeCommit message (Expand)Author
2018-11-07Add firrtl.options testsSchuyler Eldridge
2018-11-05Better error message for UninferredWidth exceptionSchuyler Eldridge
2018-11-05Add prettyPrint method to TargetSchuyler Eldridge
2018-11-02Fix renaming in UniquifyPorts (#930)Albert Chen
2018-10-31Remove all uses of get_flip and deprecateJack Koenig
2018-10-31Don't include verilog header files in "FileList" for VCS/Verilator. (#918)Jim Lawson
2018-10-30Instance Annotations (#926)Adam Izraelevitz
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
2018-10-24Instance Annotations (#865)Adam Izraelevitz
2018-10-24Better error message on missing BlackBox resourceSchuyler Eldridge
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
2018-10-12Verilog renaming uses "_", works on whole ASTSchuyler Eldridge
2018-10-03Inlining uses "_", respects namespacesSchuyler Eldridge
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
2018-09-27Add Utils.expandPrefixes as Prefix Unique helper (#900)Schuyler Eldridge
2018-09-26Enforce port uniqueness in Chirrtl/High ChecksSchuyler Eldridge
2018-09-26Another TopWiring Bug Fix (Multi-Level Annotations) (#889)alonamid
2018-09-13Do not remove ExtMods with no ports by default (#888)albertchen-sifive
2018-09-07Bug Fixes in TopWiring (#885)alonamid
2018-08-30Emit Verilog Comments (#874)albertchen-sifive
2018-08-23Fix NoDedupMem to be cognizant of Module scope (#876)Jack Koenig
2018-08-14Add targetDirName test (#869)Leway Colin
2018-08-08Use LinkedHashSet in propagateAnnotations (#855)albertchen-sifive
2018-08-07Make RemoveWires properly include registers in dependency graphJack Koenig
2018-07-26Support for load memory annotations in chisel (#833)Chick Markley
2018-07-20Constant prop add (#849)albertchen-sifive
2018-07-11Make InstanceGraph have deterministic and use defined iteration order (#843)Jack Koenig
2018-07-10Fix bug in zero-width renaming (#845)Jack Koenig
2018-07-10Combinational Dependency Annotation (#809)Adam Izraelevitz
2018-07-03Improve code generation for smem wmode and [w]mask ports (#834)Andrew Waterman
2018-07-02Make ZeroWidth properly rename removed empty aggregates (#839)Jack Koenig
2018-06-28Make CheckCombLoops find combinational nodes with self-edges (#837)Albert Magyar
2018-06-28Protobuf (#832)Jack Koenig
2018-06-21--infer-rw should take no argument (#829)Schuyler Eldridge
2018-06-14Fix TopWiringTests use of /tmp. (#825)Jim Lawson
2018-06-13Resolve register clock dependencies in RemoveWires (#823)Schuyler Eldridge
2018-06-11Allow escaped single quotes in RawParams (#820)Richard Lin
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
2018-06-06Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794)Chick Markley
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
2018-05-30Makes ExpandWhens preserve connect Infoschick
2018-05-29Fix pad (#817)Jack Koenig
2018-05-23Add Circuit as option to FirrtlOptions (#814)Jack Koenig
2018-05-21Fix more problems with zero width things. (#779)grebe
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
2018-05-11TopWiring Transform (#798)alonamid
2018-05-09Bugfix: ports of a temporary name would break const-prop (#806)Adam Izraelevitz
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
2018-04-11Cleaning up BlackBoxSourceHelper (#786)Henry Cook
2018-04-11Make DiGraph.linearize be iterative instead of recursive (#785)Jack Koenig
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