diff options
| author | Schuyler Eldridge | 2018-10-05 13:12:17 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-10-12 12:44:14 -0400 |
| commit | d426eb766a6177a3488da36ec380df47610c483a (patch) | |
| tree | cf854db621b4eb11304b180c094d1e6ca455136f /src/test | |
| parent | 95d907bd87da1f339264633f12d40673aa7e2818 (diff) | |
Refactor VerilogRename -> RemoveKeywordCollisions
This moves VerilogRename out of Passes.scala and genericizes it as the new
Transform KemoveKeywordCollisions. This new Transform will remove keywords
for arbitrary sets of reserved keyword.
This adds VerilogRename back as a class instead of an object.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 5bd17ac9..3b9f4702 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -9,6 +9,7 @@ import firrtl._ import firrtl.annotations._ import firrtl.ir.Circuit import firrtl.passes._ +import firrtl.transforms.VerilogRename import firrtl.Parser.IgnoreInfo import FirrtlCheckers._ @@ -262,7 +263,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec { | fork_ <= const_ |""".stripMargin val state = CircuitState(parse(input), UnknownForm, Seq.empty, None) - val output = Seq( ToWorkingIR, ResolveKinds, InferTypes, VerilogRename ) + val output = Seq( ToWorkingIR, ResolveKinds, InferTypes, new VerilogRename ) .foldLeft(state){ case (c, tx) => tx.runTransform(c) } Seq( CheckHighForm ) .foldLeft(output.circuit){ case (c, tx) => tx.run(c) } |
