diff options
| author | Schuyler Eldridge | 2018-10-25 16:40:59 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-11-05 15:58:14 -0500 |
| commit | 2fdc984223393ee4996f7f7fde8d6b12c9fe36c3 (patch) | |
| tree | 0b7ae45a3901986a40bf06abad24adf3ea6fe15d /src/test | |
| parent | a5c3589e7bd680bcf7db25e8fd3282d73c5e24ae (diff) | |
Better error message for UninferredWidth exception
This changes the CheckTypes.UniferredWidth exception to include the pretty
printed Target that was uninferred and suggests to the user that they may
have forgotten to assign to it. This changes the CheckTypes pass to
communicate the necessary Target information during AST traversal such
that when an uninferred width is found, the Target is known and available.
This also adds one test checking the message of the UniferredWidth
exception.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/WidthSpec.scala | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala index ab8cb7ac..058cc1fa 100644 --- a/src/test/scala/firrtlTests/WidthSpec.scala +++ b/src/test/scala/firrtlTests/WidthSpec.scala @@ -156,4 +156,29 @@ class WidthSpec extends FirrtlFlatSpec { executeTest(input, check, passes) } } + + behavior of "CheckWidths.UniferredWidth" + + it should "provide a good error message with a full target if a user forgets an assign" in { + val passes = Seq( + ToWorkingIR, + ResolveKinds, + InferTypes, + CheckTypes, + ResolveGenders, + InferWidths, + CheckWidths) + val input = + """|circuit Foo : + | module Foo : + | input clock : Clock + | inst bar of Bar + | module Bar : + | wire a: { b : UInt<1>, c : { d : UInt<1>, e : UInt } } + |""".stripMargin + val msg = intercept[CheckWidths.UninferredWidth] { executeTest(input, Nil, passes) } + .getMessage should include ("""| circuit Foo: + | └── module Bar: + | └── a.c.e""".stripMargin) + } } |
