diff options
| author | Schuyler Eldridge | 2018-11-05 12:10:21 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-11-05 15:57:43 -0500 |
| commit | a5c3589e7bd680bcf7db25e8fd3282d73c5e24ae (patch) | |
| tree | ba71817c8d30f79dcdad031eae0633281ecc3a6a /src/test | |
| parent | 3935914116d7289a8b545cc8d758785d9f8dcd13 (diff) | |
Add prettyPrint method to Target
This adds a pretty printer for firrtl.annotation.Target and associated
tests. This uses a tree-like output where the following target
~Circuit|Module/foo:Foo>ref.field[0] will serialize to:
circuit Circuit:
└── module Module:
└── foo of Foo:
└── ref.field[0]
This enables better error messages and a human readable syntax better than
the existing serialize method (and avoiding the need for users to
understand the Target serialization syntax), but that is not intended to
be deserialized nor space efficient.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/annotationTests/TargetSpec.scala | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala index 4ae4e036..da154b6a 100644 --- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala @@ -55,5 +55,31 @@ class TargetSpec extends FirrtlPropSpec { assert(Target.deserialize(t.serialize) == t, s"$t does not properly serialize/deserialize") } } + property("Pretty Printer should work") { + val circuit = CircuitTarget("A") + val top = circuit.module("B") + val targets = Seq( + (circuit, "circuit A:"), + (top, + """|circuit A: + |└── module B:""".stripMargin), + (top.instOf("c", "C"), + """|circuit A: + |└── module B: + | └── inst c of C:""".stripMargin), + (top.ref("r"), + """|circuit A: + |└── module B: + | └── r""".stripMargin), + (top.ref("r").index(1).field("hi").clock, + """|circuit A: + |└── module B: + | └── r[1].hi@clock""".stripMargin), + (GenericTarget(None, None, Vector(Ref("r"))), + """|circuit ???: + |└── module ???: + | └── r""".stripMargin) + ) + targets.foreach { case (t, str) => assert(t.prettyPrint() == str, s"$t didn't properly prettyPrint") } + } } - |
