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AgeCommit message (Expand)Author
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
2021-03-27Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)Jiuyang Liu
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
2021-03-18Ensure InlineCasts does not inline complex Expressions (#2130)Jack Koenig
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
2021-03-14Fix width of constant propagation of SInt with zero (#2120)Jack Koenig
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
2021-03-11Fix CSESubAccesses for SubAccesses with flips (#2112)Jack Koenig
2021-03-09Fix the readmem statements in nested block (#2109)Carlos Eduardo
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
2021-03-09SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)Kevin Laeufer
2021-03-08SMT: memory port inout fields cannot be used as RHS expressions (#2105)Kevin Laeufer
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
2021-03-04CSE SubAccesses (#2099)Jack Koenig
2021-03-03Fix ProtoBuf conversions for Verification IR (#2100)Deborah Soung
2021-03-02Remove Scala 2.11 (#2062)Jack Koenig
2021-02-25Emit space after 'if' for all Verilog conditional synchronous assignments (#2...Albert Magyar
2021-02-17ExpandWhens: ensure that statement names are maintained (#2082)Kevin Laeufer
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
2021-02-16Add MustDeduplicateTransformJack Koenig
2021-02-16Add DiGraph factory method and prettyTreeJack Koenig
2021-02-03IR: turn some IR nodes into data classes (#2071)Kevin Laeufer
2021-02-01Suport ir.SubAccess in Utils.splitRef (#2021)Schuyler Eldridge
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
2021-02-01ConstantPropagation: make RemoveValidIf an optional dependency (#2027)Kevin Laeufer
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
2021-01-26Fix post-merge publishing (#2055)Jack Koenig
2021-01-20Cleanup some warnings (#2032)Jack Koenig
2021-01-20Add --dont-fold option to disable folding prim ops (#2040)Schuyler Eldridge
2021-01-19Restore scalafmt CI check (#2047)Jack Koenig
2021-01-19smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)Kevin Laeufer
2020-12-15Improve performance of LowerTypes renaming (#2024)Jack Koenig
2020-12-11fix scaladoc for ReferenceTarget (#2014)Megan Wachs
2020-12-10Add newline in the end of LoFIRRTL file (#2015)XinJun Ma
2020-12-02smt: add support for uninterpreted ext modules (#1994)Kevin Laeufer
2020-12-02Fix subaccess (#1984)Jiuyang Liu
2020-11-30Add SortModules Transform (#1905)Schuyler Eldridge
2020-11-23add weak and strong to Utils.v_keywords (#1983)Tim Snyder
2020-11-17Make MultiTargetAnnotation.targets a def (#1969)Jack Koenig
2020-11-16make LazyLogging log to console by default. (#1961)Jiuyang Liu
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
2020-11-11smt: add support for write-first memories (#1948)Kevin Laeufer
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
2020-11-10Refactor emiter (#1879)Jiuyang Liu
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
2020-11-07-full64 is required to detect VCS. (#1930)Jiuyang Liu
2020-11-04Remove caching from RenameMap (#1938)Jack Koenig
2020-10-26bug fix for VerilogPrep using wrong type.Jiuyang liu
2020-10-13Make {Stage, FirrtlStage}.run protected (#1926)Schuyler Eldridge
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