diff options
| author | Jack Koenig | 2021-01-28 18:39:57 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-28 18:39:57 -0800 |
| commit | 651fbe9339aca5fcb562715d00b1f87cf66296ee (patch) | |
| tree | fc9289f3dc223db85d3fe2d67c593e87b97e19d0 /src/main | |
| parent | aec9e9e61f9b6775bf313601ec5a44a34f608609 (diff) | |
Stop padding multiply and divide ops (#2058)
Fixes bug with mul or div followed by cat.
Also fixes some Verilog lint issues.
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/PadWidths.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala index 875e80ae..1a430778 100644 --- a/src/main/scala/firrtl/passes/PadWidths.scala +++ b/src/main/scala/firrtl/passes/PadWidths.scala @@ -58,7 +58,7 @@ object PadWidths extends Pass { case ex: ValidIf => ex.copy(value = fixup(width(ex.tpe))(ex.value)) case ex: DoPrim => ex.op match { - case Lt | Leq | Gt | Geq | Eq | Neq | Not | And | Or | Xor | Add | Sub | Mul | Div | Rem | Shr => + case Lt | Leq | Gt | Geq | Eq | Neq | Not | And | Or | Xor | Add | Sub | Rem | Shr => // sensitive ops ex.map(fixup((ex.args.map(width).foldLeft(0))(math.max))) case Dshl => |