From 651fbe9339aca5fcb562715d00b1f87cf66296ee Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Thu, 28 Jan 2021 18:39:57 -0800
Subject: Stop padding multiply and divide ops (#2058)

Fixes bug with mul or div followed by cat.
Also fixes some Verilog lint issues.---
 src/main/scala/firrtl/passes/PadWidths.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 875e80ae..1a430778 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -58,7 +58,7 @@ object PadWidths extends Pass {
     case ex: ValidIf => ex.copy(value = fixup(width(ex.tpe))(ex.value))
     case ex: DoPrim =>
       ex.op match {
-        case Lt | Leq | Gt | Geq | Eq | Neq | Not | And | Or | Xor | Add | Sub | Mul | Div | Rem | Shr =>
+        case Lt | Leq | Gt | Geq | Eq | Neq | Not | And | Or | Xor | Add | Sub | Rem | Shr =>
           // sensitive ops
           ex.map(fixup((ex.args.map(width).foldLeft(0))(math.max)))
         case Dshl =>
-- 
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