aboutsummaryrefslogtreecommitdiff
path: root/src/main
diff options
context:
space:
mode:
authorJack Koenig2021-01-19 16:47:26 -0800
committerGitHub2021-01-19 16:47:26 -0800
commit6d8e9041e000f9ea5fb3d069d1f9ec06d2158575 (patch)
treece90469dbd95ba9f833aba93baa98752a16c0711 /src/main
parent0748d0458c30a5d58198080aca36b43c09184841 (diff)
Restore scalafmt CI check (#2047)
Fix scalafmtCheckAll failures that snuck through
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystem.scala12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystem.scala b/src/main/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystem.scala
index 9c309917..c1857667 100644
--- a/src/main/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystem.scala
+++ b/src/main/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystem.scala
@@ -11,7 +11,17 @@ import firrtl.passes.PassException
import firrtl.stage.Forms
import firrtl.stage.TransformManager.TransformDependency
import firrtl.transforms.{DeadCodeElimination, PropagatePresetAnnotations}
-import firrtl.{CircuitState, DependencyAPIMigration, MemoryArrayInit, MemoryInitValue, MemoryScalarInit, Namespace, Transform, Utils, ir}
+import firrtl.{
+ ir,
+ CircuitState,
+ DependencyAPIMigration,
+ MemoryArrayInit,
+ MemoryInitValue,
+ MemoryScalarInit,
+ Namespace,
+ Transform,
+ Utils
+}
import logger.LazyLogging
import scala.collection.mutable