Fix the readmem statements in nested block (#2109)

1 files changed, 1 insertions, 5 deletions

diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
index bc4996df..c7143f5f 100644
--- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
+++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
@@ -854,11 +854,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
             case MemoryLoadFileType.Binary => "$readmemb"
             case MemoryLoadFileType.Hex    => "$readmemh"
           }
-          val inlineLoad = s"""
-                              |initial begin
-                              |  $readmem("$filename", ${s.name});
-                              |end""".stripMargin
-          memoryInitials += Seq(inlineLoad)
+          memoryInitials += Seq(s"""$readmem("$filename", ${s.name});""")
       }
     }