Cleanup some warnings (#2032)

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

15 files changed, 41 insertions, 25 deletions

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index b4629a2a..38b71f4a 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -116,6 +116,14 @@ sealed abstract class CircuitForm(private val value: Int) extends Ordered[Circui
   /** Defines a suffix to use if this form is written to a file */
   def outputSuffix: String
 }
+private[firrtl] object CircuitForm {
+  // Private internal utils to reduce number of deprecation warnings
+  val ChirrtlForm = firrtl.ChirrtlForm
+  val HighForm = firrtl.HighForm
+  val MidForm = firrtl.MidForm
+  val LowForm = firrtl.LowForm
+  val UnknownForm = firrtl.UnknownForm
+}
 
 // These magic numbers give an ordering to CircuitForm
 /** Chirrtl Form
@@ -310,7 +318,7 @@ trait Transform extends TransformLike[CircuitState] with DependencyAPI[Transform
 
   def transform(state: CircuitState): CircuitState = execute(state)
 
-  import firrtl.{ChirrtlForm => C, HighForm => H, MidForm => M, LowForm => L, UnknownForm => U}
+  import firrtl.CircuitForm.{ChirrtlForm => C, HighForm => H, MidForm => M, LowForm => L, UnknownForm => U}
 
   override def prerequisites: Seq[Dependency[Transform]] = inputForm match {
     case C => Nil
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 467552cb..886ee986 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -632,7 +632,6 @@ object Utils extends LazyLogging {
   def get_flow(s: Statement): Flow = s match {
     case sx: DefWire        => DuplexFlow
     case sx: DefRegister    => DuplexFlow
-    case sx: WDefInstance   => SourceFlow
     case sx: DefNode        => SourceFlow
     case sx: DefInstance    => SourceFlow
     case sx: DefMemory      => SourceFlow
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 7ba8a0bf..dadcac46 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -164,12 +164,12 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w
                 }
                 IntervalType(UnknownBound, UnknownBound, point)
               case 2 =>
-                val lower = (ctx.lowerBound.getText, ctx.boundValue(0).getText) match {
+                val lower = ((ctx.lowerBound.getText, ctx.boundValue(0).getText): @unchecked) match {
                   case (_, "?") => UnknownBound
                   case ("(", v) => Open(string2BigDecimal(v))
                   case ("[", v) => Closed(string2BigDecimal(v))
                 }
-                val upper = (ctx.upperBound.getText, ctx.boundValue(1).getText) match {
+                val upper = ((ctx.upperBound.getText, ctx.boundValue(1).getText): @unchecked) match {
                   case (_, "?") => UnknownBound
                   case (")", v) => Open(string2BigDecimal(v))
                   case ("]", v) => Closed(string2BigDecimal(v))
diff --git a/src/main/scala/firrtl/analyses/ConnectionGraph.scala b/src/main/scala/firrtl/analyses/ConnectionGraph.scala
index e5e3bde2..32bb1564 100644
--- a/src/main/scala/firrtl/analyses/ConnectionGraph.scala
+++ b/src/main/scala/firrtl/analyses/ConnectionGraph.scala
@@ -416,6 +416,7 @@ object ConnectionGraph {
         case firrtl.ir.Field(name, Default, tpe) => Utils.create_exps(Reference(name, tpe, PortKind, SourceFlow))
         // Module input
         case firrtl.ir.Field(name, Flip, tpe) => Utils.create_exps(Reference(name, tpe, PortKind, SinkFlow))
+        case x                                => Utils.error(s"Unexpected flip: ${x.flip}")
       }
       assert(instPorts.size == modulePorts.size)
       val o = m.circuitTarget.module(ofModule)
diff --git a/src/main/scala/firrtl/analyses/InstanceGraph.scala b/src/main/scala/firrtl/analyses/InstanceGraph.scala
index 0017ff8b..8858c4ea 100644
--- a/src/main/scala/firrtl/analyses/InstanceGraph.scala
+++ b/src/main/scala/firrtl/analyses/InstanceGraph.scala
@@ -185,7 +185,6 @@ object InstanceGraph {
   @deprecated("Use InstanceKeyGraph.collectInstances instead.", "FIRRTL 1.4")
   def collectInstances(insts: mutable.Set[DefInstance])(s: Statement): Unit = s match {
     case i: DefInstance           => insts += i
-    case i: DefInstance           => throwInternalError("Expecting DefInstance, found a DefInstance!")
     case i: WDefInstanceConnector => throwInternalError("Expecting DefInstance, found a DefInstanceConnector!")
     case _ => s.foreach(collectInstances(insts))
   }
diff --git a/src/main/scala/firrtl/annotations/Annotation.scala b/src/main/scala/firrtl/annotations/Annotation.scala
index 5f792127..b5c9c7e0 100644
--- a/src/main/scala/firrtl/annotations/Annotation.scala
+++ b/src/main/scala/firrtl/annotations/Annotation.scala
@@ -71,7 +71,7 @@ trait SingleTargetAnnotation[T <: Named] extends Annotation {
               case c: CircuitTarget => c.toNamed
               case other => throw Target.NamedException(s"Cannot convert $other to [[Named]]")
             }
-            Target.convertTarget2Named(result) match {
+            (Target.convertTarget2Named(result): @unchecked) match {
               case newTarget: T @unchecked =>
                 try {
                   duplicate(newTarget)
diff --git a/src/main/scala/firrtl/annotations/Target.scala b/src/main/scala/firrtl/annotations/Target.scala
index 8e84a269..92339946 100644
--- a/src/main/scala/firrtl/annotations/Target.scala
+++ b/src/main/scala/firrtl/annotations/Target.scala
@@ -265,7 +265,7 @@ case class GenericTarget(circuitOpt: Option[String], moduleOpt: Option[String],
         case GenericTarget(Some(c), Some(m), Instance(i) +: OfModule(o) +: Vector()) => InstanceTarget(c, m, Nil, i, o)
         case GenericTarget(Some(c), Some(m), component) =>
           val path = getPath.getOrElse(Nil)
-          (getRef, getInstanceOf) match {
+          ((getRef, getInstanceOf): @unchecked) match {
             case (Some((r, comps)), _) => ReferenceTarget(c, m, path, r, comps)
             case (None, Some((i, o)))  => InstanceTarget(c, m, path, i, o)
           }
@@ -516,6 +516,7 @@ trait IsComponent extends IsMember {
             case ("", Ref(name))        => name
             case (string, Field(value)) => s"$string.$value"
             case (string, Index(value)) => s"$string[$value]"
+            case (_, token)             => Utils.error(s"Unexpected token: $token")
           }
           ComponentName(name, mn)
         case Seq(Instance(name), OfModule(o)) => ComponentName(name, mn)
@@ -660,6 +661,7 @@ case class ReferenceTarget(
         case Index(idx)   => sub_type(baseType)
         case Field(field) => field_type(baseType, field)
         case _: Ref => baseType
+        case token => Utils.error(s"Unexpected token $token")
       }
       componentType(headType, tokens.tail)
     }
diff --git a/src/main/scala/firrtl/backends/firrtl/FirrtlEmitter.scala b/src/main/scala/firrtl/backends/firrtl/FirrtlEmitter.scala
index 26e03633..80aea996 100644
--- a/src/main/scala/firrtl/backends/firrtl/FirrtlEmitter.scala
+++ b/src/main/scala/firrtl/backends/firrtl/FirrtlEmitter.scala
@@ -20,8 +20,7 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
       // Use list instead of set to maintain order
       val modules = mutable.ArrayBuffer.empty[DefModule]
       def onStmt(stmt: Statement): Unit = stmt match {
-        case DefInstance(_, _, name, _)  => modules += map(name)
-        case WDefInstance(_, _, name, _) => modules += map(name)
+        case DefInstance(_, _, name, _) => modules += map(name)
         case _: WDefInstanceConnector => throwInternalError(s"unrecognized statement: $stmt")
         case other => other.foreach(onStmt)
       }
@@ -61,7 +60,7 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
   def emit(state: CircuitState, writer: Writer): Unit = writer.write(state.circuit.serialize)
 }
 
-class ChirrtlEmitter extends FirrtlEmitter(ChirrtlForm)
-class HighFirrtlEmitter extends FirrtlEmitter(HighForm)
-class MiddleFirrtlEmitter extends FirrtlEmitter(MidForm)
-class LowFirrtlEmitter extends FirrtlEmitter(LowForm)
+class ChirrtlEmitter extends FirrtlEmitter(CircuitForm.ChirrtlForm)
+class HighFirrtlEmitter extends FirrtlEmitter(CircuitForm.HighForm)
+class MiddleFirrtlEmitter extends FirrtlEmitter(CircuitForm.MidForm)
+class LowFirrtlEmitter extends FirrtlEmitter(CircuitForm.LowForm)
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index a26a2a94..7d091176 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -891,6 +891,7 @@ case class IntervalType(lower: Bound, upper: Bound, point: Width) extends Ground
         case x                    => Some(x.setScale(0, FLOOR) * prec)
       }
     case (Closed(a), Some(prec)) => Some((a / prec).setScale(0, FLOOR) * prec)
+    case _                       => None
   }
 
   def minAdjusted: Option[BigInt] = min.map(_ * BigDecimal(BigInt(1) << bp) match {
diff --git a/src/main/scala/firrtl/passes/CInferMDir.scala b/src/main/scala/firrtl/passes/CInferMDir.scala
index 90f1c739..cca8fde4 100644
--- a/src/main/scala/firrtl/passes/CInferMDir.scala
+++ b/src/main/scala/firrtl/passes/CInferMDir.scala
@@ -22,22 +22,19 @@ object CInferMDir extends Pass {
         case None =>
         case Some(p) =>
           mports(e.name) = (p, dir) match {
-            case (MInfer, MInfer)         => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
             case (MInfer, MWrite)         => MWrite
             case (MInfer, MRead)          => MRead
             case (MInfer, MReadWrite)     => MReadWrite
-            case (MWrite, MInfer)         => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
             case (MWrite, MWrite)         => MWrite
             case (MWrite, MRead)          => MReadWrite
             case (MWrite, MReadWrite)     => MReadWrite
-            case (MRead, MInfer)          => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
             case (MRead, MWrite)          => MReadWrite
             case (MRead, MRead)           => MRead
             case (MRead, MReadWrite)      => MReadWrite
-            case (MReadWrite, MInfer)     => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
             case (MReadWrite, MWrite)     => MReadWrite
             case (MReadWrite, MRead)      => MReadWrite
             case (MReadWrite, MReadWrite) => MReadWrite
+            case _                        => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir")
           }
       }
       e
diff --git a/src/main/scala/firrtl/passes/CheckHighForm.scala b/src/main/scala/firrtl/passes/CheckHighForm.scala
index 5514741a..7e305b33 100644
--- a/src/main/scala/firrtl/passes/CheckHighForm.scala
+++ b/src/main/scala/firrtl/passes/CheckHighForm.scala
@@ -243,8 +243,7 @@ trait CheckHighFormLike { this: Pass =>
           errors.append(new NegUIntException(info, mname))
         case ex: DoPrim => checkHighFormPrimop(info, mname, ex)
         case _: Reference | _: WRef | _: UIntLiteral | _: Mux | _: ValidIf =>
-        case ex: SubAccess  => validSubexp(info, mname)(ex.expr)
-        case ex: WSubAccess => validSubexp(info, mname)(ex.expr)
+        case ex: SubAccess => validSubexp(info, mname)(ex.expr)
         case ex => ex.foreach(validSubexp(info, mname))
       }
       e.foreach(checkHighFormW(info, mname + "/" + e.serialize))
@@ -284,7 +283,6 @@ trait CheckHighFormLike { this: Pass =>
           if (sx.depth <= 0)
             errors.append(new NegMemSizeException(info, mname))
         case sx:    DefInstance    => checkInstance(info, mname, sx.module)
-        case sx:    WDefInstance   => checkInstance(info, mname, sx.module)
         case sx:    Connect        => checkValidLoc(info, mname, sx.loc)
         case sx:    PartialConnect => checkValidLoc(info, mname, sx.loc)
         case sx:    Print          => checkFstring(info, mname, sx.string, sx.args.length)
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index aa2095fa..56cd4dd2 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -110,6 +110,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths with Dependency
     case (AsyncResetType, AsyncResetType) => Nil
     case (ResetType, _)                   => Nil
     case (_, ResetType)                   => Nil
+    case _                                => throwInternalError("Shouldn't be here")
   }
 
   private def addExpConstraints(e: Expression)(implicit constraintSolver: ConstraintSolver): Expression =
diff --git a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
index 9ad653cf..671a08b9 100644
--- a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
+++ b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
@@ -16,7 +16,6 @@ object RemoveAllButClocks extends Pass {
     case DefWire(i, n, ClockType)                       => s
     case DefNode(i, n, value) if value.tpe == ClockType => s
     case Connect(i, l, r) if l.tpe == ClockType         => s
-    case sx: WDefInstance  => sx
     case sx: DefInstance   => sx
     case sx: Block         => sx
     case sx: Conditionally => sx
diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
index d926f6a9..cab6aa5f 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
@@ -90,8 +90,6 @@ object WiringUtils {
   def getChildrenMap(c: Circuit): ChildrenMap = {
     val childrenMap = new ChildrenMap()
     def getChildren(mname: String)(s: Statement): Unit = s match {
-      case s: WDefInstance =>
-        childrenMap(mname) = childrenMap(mname) :+ ((s.name, s.module))
       case s: DefInstance =>
         childrenMap(mname) = childrenMap(mname) :+ ((s.name, s.module))
       case s => s.foreach(getChildren(mname))
diff --git a/src/main/scala/firrtl/proto/FromProto.scala b/src/main/scala/firrtl/proto/FromProto.scala
index 663e91b3..cb9b705e 100644
--- a/src/main/scala/firrtl/proto/FromProto.scala
+++ b/src/main/scala/firrtl/proto/FromProto.scala
@@ -148,6 +148,9 @@ object FromProto {
     case ReadUnderWrite.UNDEFINED => ir.ReadUnderWrite.Undefined
     case ReadUnderWrite.OLD       => ir.ReadUnderWrite.Old
     case ReadUnderWrite.NEW       => ir.ReadUnderWrite.New
+    case ReadUnderWrite.UNRECOGNIZED =>
+      val msg = s"Unrecognized ReadUnderWrite value '$ruw', perhaps this version of FIRRTL is too old?"
+      throw new FirrtlUserException(msg)
   }
 
   def convert(dt: Firrtl.Statement.CMemory.TypeAndDepth): (ir.Type, BigInt) =
@@ -171,6 +174,10 @@ object FromProto {
     case MEMORY_PORT_DIRECTION_READ       => MRead
     case MEMORY_PORT_DIRECTION_WRITE      => MWrite
     case MEMORY_PORT_DIRECTION_READ_WRITE => MReadWrite
+    case MEMORY_PORT_DIRECTION_UNKNOWN    => MInfer
+    case UNRECOGNIZED =>
+      val msg = s"Unrecognized MemoryPort Direction value '$mportdir', perhaps this version of FIRRTL is too old?"
+      throw new FirrtlUserException(msg)
   }
 
   def convert(port: Firrtl.Statement.MemoryPort, info: Firrtl.SourceInfo): CDefMPort = {
@@ -191,6 +198,9 @@ object FromProto {
     case Formal.ASSERT => ir.Formal.Assert
     case Formal.ASSUME => ir.Formal.Assume
     case Formal.COVER  => ir.Formal.Cover
+    case Formal.UNRECOGNIZED =>
+      val msg = s"Unrecognized Formal value '$formal', perhaps this version of FIRRTL is too old?"
+      throw new FirrtlUserException(msg)
   }
 
   def convert(ver: Firrtl.Statement.Verification, info: Firrtl.SourceInfo): ir.Verification =
@@ -308,9 +318,13 @@ object FromProto {
   }
 
   def convert(dir: Firrtl.Port.Direction): ir.Direction = {
+    import Firrtl.Port.Direction._
     dir match {
-      case Firrtl.Port.Direction.PORT_DIRECTION_IN  => ir.Input
-      case Firrtl.Port.Direction.PORT_DIRECTION_OUT => ir.Output
+      case PORT_DIRECTION_IN  => ir.Input
+      case PORT_DIRECTION_OUT => ir.Output
+      case (PORT_DIRECTION_UNKNOWN | UNRECOGNIZED) =>
+        val msg = s"Unrecognized Port Direction value '$dir', perhaps this version of FIRRTL is too old?"
+        throw new FirrtlUserException(msg)
     }
   }