Added sequential/combinational memories. Started debugging verilog backend. Added Long support so UInt(LARGENUMBER) works

24 files changed, 40 insertions, 40 deletions

diff --git a/test/chisel3/ALUTop.fir b/test/chisel3/ALUTop.fir
index b9386349..5ebcbccc 100644
--- a/test/chisel3/ALUTop.fir
+++ b/test/chisel3/ALUTop.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit ALUTop : 
diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir
index 2c2ad772..eeed3309 100644
--- a/test/chisel3/BundleWire.fir
+++ b/test/chisel3/BundleWire.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit BundleWire : 
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir
index c1dc41cd..925b8e34 100644
--- a/test/chisel3/ComplexAssign.fir
+++ b/test/chisel3/ComplexAssign.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit ComplexAssign : 
diff --git a/test/chisel3/Control.fir b/test/chisel3/Control.fir
index 2d109102..28bb3d87 100644
--- a/test/chisel3/Control.fir
+++ b/test/chisel3/Control.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Control : 
diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir
index b81eb7e9..06010573 100644
--- a/test/chisel3/Core.fir
+++ b/test/chisel3/Core.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Core : 
@@ -97,7 +97,7 @@ circuit Core :
     input waddr : UInt<5>
     input wdata : UInt<32>
     
-    mem regs : UInt<32>[32]
+    cmem regs : UInt<32>[32]
     node T_1286 = eq(raddr1, UInt<1>(0))
     node T_1287 = bit-not(T_1286)
     accessor T_1288 = regs[raddr1]
diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir
index 6f04dfb9..0f80f687 100644
--- a/test/chisel3/Counter.fir
+++ b/test/chisel3/Counter.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Counter : 
diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir
index ef62df98..10643549 100644
--- a/test/chisel3/Datapath.fir
+++ b/test/chisel3/Datapath.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Datapath : 
@@ -97,7 +97,7 @@ circuit Datapath :
     input waddr : UInt<5>
     input wdata : UInt<32>
     
-    mem regs : UInt<32>[32]
+    cmem regs : UInt<32>[32]
     node T_495 = eq(raddr1, UInt<1>(0))
     node T_496 = bit-not(T_495)
     accessor T_497 = regs[raddr1]
diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir
index 795b03e4..bfc8f9c3 100644
--- a/test/chisel3/EnableShiftRegister.fir
+++ b/test/chisel3/EnableShiftRegister.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit EnableShiftRegister : 
diff --git a/test/chisel3/GCD.fir b/test/chisel3/GCD.fir
index d6f7d798..90b0a8b8 100644
--- a/test/chisel3/GCD.fir
+++ b/test/chisel3/GCD.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit GCD : 
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
index cdf1b835..29a2823a 100644
--- a/test/chisel3/LFSR16.fir
+++ b/test/chisel3/LFSR16.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit LFSR16 : 
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir
index 375bfcff..a0cc0b7d 100644
--- a/test/chisel3/MemorySearch.fir
+++ b/test/chisel3/MemorySearch.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit MemorySearch : 
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 87d0fed0..758f544c 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit ModuleVec : 
diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir
index fefe42bd..3be7f928 100644
--- a/test/chisel3/ModuleWire.fir
+++ b/test/chisel3/ModuleWire.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit ModuleWire : 
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index fab610b6..c5dccb6f 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Mul : 
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
index a7631277..886a01ba 100644
--- a/test/chisel3/Outer.fir
+++ b/test/chisel3/Outer.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Outer : 
diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir
index 3a9658eb..3d51ece3 100644
--- a/test/chisel3/RegisterVecShift.fir
+++ b/test/chisel3/RegisterVecShift.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit RegisterVecShift : 
diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir
index bd02bac3..425f8a91 100644
--- a/test/chisel3/Risc.fir
+++ b/test/chisel3/Risc.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Risc : 
@@ -10,8 +10,8 @@ circuit Risc :
     input wrAddr : UInt<8>
     input wrData : UInt<32>
     
-    mem file : UInt<32>[256]
-    mem code : UInt<32>[256]
+    cmem file : UInt<32>[256]
+    cmem code : UInt<32>[256]
     reg pc : UInt<8>
     on-reset pc := UInt<8>(0)
     accessor inst = code[pc]
diff --git a/test/chisel3/Rom.fir b/test/chisel3/Rom.fir
index 8e80b7d4..1c19d9b3 100644
--- a/test/chisel3/Rom.fir
+++ b/test/chisel3/Rom.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Rom : 
diff --git a/test/chisel3/SIntOps.fir b/test/chisel3/SIntOps.fir
index ee1aa366..59ad2a47 100644
--- a/test/chisel3/SIntOps.fir
+++ b/test/chisel3/SIntOps.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit SIntOps : 
@@ -26,15 +26,15 @@ circuit SIntOps :
     node T_39 = sub-wrap(a, b)
     subout := T_39
     node T_40 = mul(a, b)
-    node T_41 = bits(T_40, 15, 0)
-    timesout := T_41
+    node T_41 = bits(as-UInt(T_40), 15, 0)
+    timesout := as-SInt(T_41)
     node T_42 = mul(a, b)
-    node T_43 = bits(T_42, 15, 0)
-    divout := T_43
-    modout := UInt<1>(0)
+    node T_43 = bits(as-UInt(T_42), 15, 0)
+    divout := as-SInt(T_43)
+    modout := SInt<1>(0)
     node T_44 = shl(a, 12)
-    node T_45 = bits(T_44, 15, 0)
-    lshiftout := T_45
+    node T_45 = bits(as-UInt(T_44), 15, 0)
+    lshiftout := as-SInt(T_45)
     node T_46 = shr(a, 8)
     rshiftout := T_46
     node T_47 = lt(a, b)
diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir
index 84cb6ccd..caa70da5 100644
--- a/test/chisel3/Stack.fir
+++ b/test/chisel3/Stack.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Stack : 
@@ -9,7 +9,7 @@ circuit Stack :
     output dataOut : UInt<32>
     input dataIn : UInt<32>
     
-    mem stack_mem : UInt<32>[16]
+    cmem stack_mem : UInt<32>[16]
     reg sp : UInt<5>
     on-reset sp := UInt<5>(0)
     reg out : UInt<32>
diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir
index d64916f1..e7397f61 100644
--- a/test/chisel3/Tbl.fir
+++ b/test/chisel3/Tbl.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Tbl : 
@@ -8,7 +8,7 @@ circuit Tbl :
     output o : UInt<16>
     input we : UInt<1>
     
-    mem m : UInt<10>[256]
+    cmem m : UInt<10>[256]
     o := UInt<1>(0)
     when we : 
       accessor T_13 = m[i]
diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir
index eeec18ee..01d78cd0 100644
--- a/test/chisel3/Tile.fir
+++ b/test/chisel3/Tile.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Tile : 
@@ -97,7 +97,7 @@ circuit Tile :
     input waddr : UInt<5>
     input wdata : UInt<32>
     
-    mem regs : UInt<32>[32]
+    cmem regs : UInt<32>[32]
     node T_1616 = eq(raddr1, UInt<1>(0))
     node T_1617 = bit-not(T_1616)
     accessor T_1618 = regs[raddr1]
@@ -1026,7 +1026,7 @@ circuit Tile :
     input enq : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}}
     output deq : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}}
     
-    mem ram : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}[4]
+    cmem ram : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}[4]
     reg T_2381 : UInt<2>
     on-reset T_2381 := UInt<2>(0)
     reg T_2382 : UInt<2>
@@ -1089,7 +1089,7 @@ circuit Tile :
     input enq : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}}
     output deq : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}}
     
-    mem ram : {data : UInt<32>}[4]
+    cmem ram : {data : UInt<32>}[4]
     reg T_2412 : UInt<2>
     on-reset T_2412 := UInt<2>(0)
     reg T_2413 : UInt<2>
diff --git a/test/chisel3/UIntOps.fir b/test/chisel3/UIntOps.fir
index 9b219523..1707bbee 100644
--- a/test/chisel3/UIntOps.fir
+++ b/test/chisel3/UIntOps.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit UIntOps : 
diff --git a/test/chisel3/VendingMachine.fir b/test/chisel3/VendingMachine.fir
index a1149dbc..39723b05 100644
--- a/test/chisel3/VendingMachine.fir
+++ b/test/chisel3/VendingMachine.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit VendingMachine :