diff options
37 files changed, 1286 insertions, 82 deletions
@@ -42,6 +42,12 @@ clean: rm -f $(test_dir)/*/*/*.out rm -f $(test_dir)/*/*.out +riscv: + cd $(test_dir)/riscv-mini && lit -v . --path=$(root_dir)/utils/bin/ + +push: + scp test/riscv-mini/*.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src + done: say "done" @@ -3,14 +3,15 @@ ================================================ ======== Current Tasks ======== -SeqMem +Add print, assert move width inference earlier + Required for subword assignment, consistent vec width inference, and supporting the new constructs of tobits/frombits +Low FIRRTL pass analysis Temp elimination needs to count # uses Declared references needs to understand scope <= check in high form check Check for recursively defined instances Names in bundles must be unique Fix reset scope -Fix firrtl-gen so it is a relative pass, not global state Add Unit Tests for each pass Check after each pass write test that checks instance types are correctly lowered @@ -31,6 +32,11 @@ o 6) Emit all register updates: Notes: For now, emit mems as reg with nothing else. WritePorts? +Checks: + names in fields should be special renamed + widths are -1 of size + zero width? + ======== Update Core ========== Add vptype @@ -61,7 +67,6 @@ deadcode elimination Andrew: Way to keep Array information for backends to avoid code explosion ======== Think About ======== -<> subword accesses verilog style guide annotation system @@ -69,8 +74,6 @@ zero-width wires expanding mems (consider changing defmem to be size, and element type) Multi-streams for print statements/asserts (Jack) Consider def female node. (Patrick) -Talk to palmer/patrick about how writing passes is going to be supported -Figure out how widths propogate for all updated primops (Adam) Add FIFOs to the IR (Palmer) Think about supporting generic primops on bundles and vecs (Adam) (wait until front-end more completed) Union Types diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index efa8c992..5a2e2278 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -56,9 +56,11 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ExpandIndexedConnects() ExpandWhens() InferWidths() + Pad() SplitExp() ToRealIR() - SpecialRename(`#,`_) + SpecialRename(`#,`__) + SpecialRename(`$,`_) Verilog(file(c)) ] diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza index e4c3d9d3..3b6c28ff 100644 --- a/src/main/stanza/custom-passes.stanza +++ b/src/main/stanza/custom-passes.stanza @@ -45,7 +45,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym val sym = HashTable<Symbol,Int>(symbol-hash) val w1 = IntWidth(1) val t1 = UIntType(w1) - val u1 = UIntValue(1,w1) + val u1 = UIntValue(to-long $ 1,w1) defn when-coverage (s:Stmt) -> Stmt : match(s) : (s:Conditionally) : @@ -70,7 +70,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym if length(w-ls) != 0 : val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls)))) add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) - add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(0,IntWidth(length(w-ls)))) + add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,IntWidth(length(w-ls)))) for (x in w-ls, i in 0 to false) do : add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1))) @@ -80,7 +80,7 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Sym if length(i-ls) != 0 : for (x in i-ls, i in 0 to false) do : add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) - add{logic,_} $ Connect(FileInfo(),x,UIntValue(0,UnknownWidth())) + add{logic,_} $ Connect(FileInfo(),x,UIntValue(to-long $ 0,UnknownWidth())) if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls))) diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 0795a2a9..aff22460 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -22,11 +22,6 @@ defpackage firrtl/errors : ; o pad's width is greater than value's width ; o widths are large enough to contain value -;AFTER LOWERING -; o All things connect to once -; o no reg -; o no accessors - ;AFTER ?????? ; o No combinational loops ; o cannot connect to a pad, or a register. only connct to a reference @@ -233,9 +228,8 @@ public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit : (e:Ref|Subfield|Index) : false (e) : add(errors,InvalidIndex(info)) (e:DoPrim) : check-high-form-primop(e,errors,info) - ;; (e:UIntValue) : - ;; if value(e) < 0 : - ;; add(errors,NegUInt(info)) + (e:UIntValue) : + if value(e) < to-long $ 0 : add(errors,NegUInt(info)) (e) : false map(check-high-form-w{info,_:Width},e) map(check-high-form-t{info,_:Type},e) @@ -694,3 +688,134 @@ public defn check-genders (c:Circuit) -> Circuit : throw(PassExceptions(errors)) when not empty?(errors) c +;================= High Form Check ========================== +;AFTER LOWERING +; o All things connect to once +; o no reg +; o no accessors +; o only vecs are for memories +; o no bundles (future, will have them for mems) +; o +; +;public defstruct CheckLowForm <: Pass : +; sym : Symbol +;public defmethod pass (b:CheckLowForm) -> (Circuit -> Circuit) : check-low-form{_,sym(b)} +;public defmethod name (b:CheckLowForm) -> String : "Low Form Check" +;public defmethod short-name (b:CheckLowForm) -> String : "low-form-check" +; +;;----------------- Errors ------------------------ +;defn NotUnique (info:FileInfo, name:Symbol) : +; PassException $ string-join $ +; [info ": Reference " name " does not have a unique name."] +; +; +;;---------------- Helper Functions -------------- +; +;;--------------- Check Low Form Pass ------------------- +;public defn check-low-form (c:Circuit,sym:Symbol) -> Circuit : +; val errors = Vector<PassException>() +; +; defn check-high-form-w (info:FileInfo,w:Width) -> Width : +; match(w) : +; (w:IntWidth) : +; if width(w) < 0 : add(errors,NegWidth(info)) +; w +; (w) : w +; +; defn check-high-form-t (info:FileInfo,t:Type) -> Type : +; match(map(check-high-form-t{info,_},t)) : +; (t:VectorType) : +; if size(t) < 0 : add(errors,NegVecSize(info)) +; (t) : false +; map(check-high-form-w{info,_:Width},t) +; +; defn check-high-form-e (info:FileInfo,e:Expression,names:Vector<Symbol>) -> Expression : +; match(map(check-high-form-e{info,_,names},e)) : +; (e:Ref) : +; if not contains?(name(e),names) : +; add(errors,UndeclaredReference(info,name(e))) +; (e:Subfield) : +; match(exp(e)) : +; (e:Ref|Subfield|Index) : false +; (e) : add(errors,InvalidSubfield(info)) +; (e:Index) : +; match(exp(e)) : +; (e:Ref|Subfield|Index) : false +; (e) : add(errors,InvalidIndex(info)) +; (e:DoPrim) : check-high-form-primop(e,errors,info) +; (e:UIntValue) : +; if value(e) < to-long $ 0 : add(errors,NegUInt(info)) +; (e) : false +; map(check-high-form-w{info,_:Width},e) +; map(check-high-form-t{info,_:Type},e) +; e +; +; defn check-high-form-s (s:Stmt,names:Vector<Symbol>) -> Stmt : +; defn check-name (info:FileInfo,name:Symbol) -> False : +; if contains?(name,names) : add(errors,NotUnique(info,name)) +; val prefix = is-prefix?(name,names,sym) +; if prefix typeof Symbol : add(errors,IsPrefix(info,name,prefix as Symbol)) +; +; map(check-high-form-t{info(s),_:Type},s) +; +; map{check-high-form-s{_,names},_} $ { +; match(map(check-high-form-e{info(s),_,names},s)) : +; (s:DefWire|DefRegister) : +; check-name(info(s),name(s)) +; add(names,name(s)) +; (s:DefMemory) : +; check-name(info(s),name(s)) +; add(names,name(s)) +; if has-flip?(type(s)) : add(errors, MemWithFlip(info(s), name(s))) +; (s:DefInstance) : +; if not contains?(name(module(s) as Ref),map(name,modules(c))) : +; add(errors, ModuleNotDefined(info(s),name(module(s) as Ref))) +; check-name(info(s),name(s)) +; add(names,name(s)) +; (s:DefNode) : +; check-name(info(s),name(s)) +; add(names,name(s)) +; (s:DefAccessor) : +; check-name(info(s),name(s)) +; add(names,name(s)) +; (s:Connect) : +; check-valid-loc(info(s),loc(s)) +; (s:BulkConnect) : +; check-valid-loc(info(s),loc(s)) +; (s) : false +; s }() +; +; defn check-high-form-m (m:Module) -> False : +; val names = Vector<Symbol>() +; for m in modules(c) do : +; add(names,name(m)) +; for p in ports(m) do : +; add(names,name(p)) +; if name(p) == `reset : +; if direction(p) == OUTPUT : +; add(errors,WrongReset(info!(m),name(m))) +; else : +; if type(p) typeof UIntType : +; if width(type(p) as UIntType) != IntWidth(1) : +; add(errors,WrongReset(info!(m),name(m))) +; else : +; add(errors,WrongReset(info!(m),name(m))) +; map(check-high-form-t{info(p),_},type(p)) +; map(check-high-form-w{info(p),_},type(p)) +; +; +; +; add(names,`reset) +; match(m) : +; (m:ExModule) : false +; (m:InModule) : check-high-form-s(body(m),names) +; false +; +; var number-top-m = 0 +; for m in modules(c) do : +; if name(m) == main(c) : number-top-m = number-top-m + 1 +; check-high-form-m(m) +; if number-top-m != 1 : add(errors,NoTopModule(info!(c),main(c))) +; throw(PassExceptions(errors)) when not empty?(errors) +; c +; diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index 18e069b4..aeaecf47 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -73,10 +73,10 @@ public defstruct Index <: Expression : value: Int type: Type with: (as-method => true) public defstruct UIntValue <: Expression : - value: Int + value: Long width: Width public defstruct SIntValue <: Expression : - value: Int + value: Long width: Width public defstruct DoPrim <: Expression : op: PrimOp diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index cbfe106e..588efeac 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -81,6 +81,10 @@ defsyntax firrtl : int = (?x) when unwrap-token(x) typeof Int : unwrap-token(x) + ;Parses next form if long literal + intorlong = (?x) when unwrap-token(x) typeof Int|Long : + unwrap-token(x) + ;Parses next form if symbol sym = (?x) when unwrap-token(x) typeof Symbol : unwrap-token(x) @@ -107,6 +111,10 @@ defsyntax firrtl : int$ = (?i:#int ?rest ...) when empty?(rest) : i int$ != () : FPE(form, "Expected a single integer literal here.") + ;Error if not a single long integer + long$ = (?i:#intorlong ?rest ...) when empty?(rest) : to-long(i) + long$ != () : FPE(form, "Expected a single long integer literal here.") + ;Error if not a single width width$ = (?w:#width ?rest ...) when empty?(rest) : w width$ != () : FPE(form, "Expected a single width specifier here.") @@ -227,7 +235,7 @@ defsyntax firrtl : expop = (. ?f:#id!) : (fn (x) : Subfield(x, f, UnknownType())) ;Prefix Operators - expterm = (?t:#inttype(?v:#int$)) : + expterm = (?t:#inttype(?v:#long$)) : match(t) : (t:UIntType) : UIntValue(v, width(t)) (t:SIntType) : SIntValue(v, width(t)) diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index c39a1ad1..1d209622 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -69,7 +69,26 @@ public defmulti name (p:Pass) -> String public defmulti short-name (p:Pass) -> String public defmethod print (o:OutputStream, p:Pass) : print(o,name(p)) + +;============== Various Useful Functions ============== + +public defn ceil-log2 (i:Long) -> Long : + defn* loop (n:Long, l:Long) : + if n < i : + if l == 30 : to-long(31) + else : loop(n * to-long(2), l + to-long(1)) + else : l + error("Log of negative number!") when i < to-long(0) + loop(to-long $ 1, to-long $ 0) + +public defn abs (x:Long) -> Long : + if x < to-long(0) : to-long(0) - x + else : x + +;public defn to-int (x:Long) -> Int : + ;if x > to-long(2147483647) or x < to-long(–2147483648) : error("Long too big to convert to Int") + ;else : x + 0 ;============== PRINTERS =================================== diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 80035325..fb889cf4 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -999,7 +999,7 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt : to-list $ for (i in 0 to false, l in locs(s)) stream : Conditionally( info(s), - equality(ref,UIntValue(i,UnknownWidth())), + equality(ref,UIntValue(to-long $ i,UnknownWidth())), Connect(info(s),l,exp(s)), EmptyStmt() ) @@ -1013,7 +1013,7 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt : to-list $ for (i in 1 to false, e in tail(exps(s))) stream : Conditionally( info(s), - equality(ref,UIntValue(i,UnknownWidth())), + equality(ref,UIntValue(to-long $ i,UnknownWidth())), Connect(info(s),loc(s),e), EmptyStmt() ) @@ -1059,8 +1059,8 @@ public defmethod short-name (b:ExpandWhens) -> String : "expand-whens" ; ======== Expression Computation Library =========== -val zero = UIntValue(0,IntWidth(1)) -val one = UIntValue(1,IntWidth(1)) +val zero = UIntValue(to-long $ 0,IntWidth(1)) +val one = UIntValue(to-long $ 1,IntWidth(1)) defmethod equal? (e1:Expression,e2:Expression) -> True|False : match(e1,e2) : @@ -1501,7 +1501,6 @@ defmethod equal? (w1:Width,w2:Width) -> True|False : defn apply (a:Int|False,b:Int|False, f: (Int,Int) -> Int) -> Int|False : if a typeof Int and b typeof Int : f(a as Int, b as Int) else : false - defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> : defn contains? (n:Symbol,h:HashTable<Symbol,?>) -> True|False : key?(h,n) @@ -1682,14 +1681,14 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod match(width(e)) : (w:UnknownWidth) : val w* = VarWidth(firrtl-gensym(`w,width-name-hash)) - add(v,WGeq(w*,IntWidth(ceil-log2(value(e))))) + add(v,WGeq(w*,IntWidth(to-int $ to-string $ ceil-log2(value(e))))) UIntValue(value(e),w*) (w) : e (e:SIntValue) : match(width(e)) : (w:UnknownWidth) : val w* = VarWidth(firrtl-gensym(`w,width-name-hash)) - add(v,WGeq(w*,IntWidth(1 + ceil-log2(abs(value(e)))))) + add(v,WGeq(w*,IntWidth(1 + to-int $ to-string $ ceil-log2(abs(value(e)))))) SIntValue(value(e),w*) (w) : e (e) : e @@ -1869,10 +1868,10 @@ public defmethod pass (b:SplitExp) -> (Circuit -> Circuit) : split-exp public defmethod name (b:SplitExp) -> String : "Split Expressions" public defmethod short-name (b:SplitExp) -> String : "split-expressions" -defn full-name (e:Expression) -> Symbol : +defn full-name (e:Expression) -> Symbol|False : match(e) : (e:WRef) : name(e) - (e:WSubfield) : to-symbol $ string-join([full-name(exp(e)) "." name(e)]) + (e:WSubfield) : false (e) : error("Non-supported expression.") defn split-exp (c:Circuit) : @@ -1959,19 +1958,26 @@ public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) : else : if substring(st,0,length(os)) == os : add(y,ns) + println(st) + println(substring(st,length(os),length(st))) rename(substring(st,length(os),length(st))) else : add(y,substring(st,0,1)) rename(substring(st,1,length(st))) rename(to-string(s)) to-symbol $ string-join $ to-list(y) + defn to-type (t:Type) -> Type : + match(map(to-type,t)) : + (t:BundleType) : BundleType $ + for f in fields(t) map : Field(rename(name(f)),flip(f),type(f)) + (t) : t defn to-exp (e:Expression) -> Expression : - match(map(to-exp,e)) : + map{to-type,_} $ match(map(to-exp,e)) : (e:Ref) : Ref(rename(name(e)), type(e)) (e:Subfield) : Subfield(exp(e),rename(name(e)),type(e)) (e) : e defn to-stmt (s:Stmt) -> Stmt : - match(map(to-exp,s)) : + map{to-type,_} $ match(map(to-exp,s)) : (s:DefWire) : DefWire(info(s),rename(name(s)),type(s)) (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s)) (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s)) diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index bee10177..50ea1fc1 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -24,7 +24,10 @@ defn width! (t:Type) -> Int : defn emit (w:Width) -> String : match(w) : - (w:IntWidth) : string-join $ ["[" width(w) ":0]"] ;TODO check if need to special case 0 or 1 width wires + (w:IntWidth) : + if width(w) >= 1 : string-join $ ["[" width(w) - 1 ":0]"] ;TODO check if need to special case 0 or 1 width wires + else : "" + (w) : error("Non-supported width type.") defn get-width (t:Type) -> String : @@ -77,15 +80,15 @@ defn emit (e:Expression) -> String : val x = args(e)[0] val w = width!(type(x)) val diff = consts(e)[0] - w - ["{" diff "{" x "[" w - 1 "]}," emit(x)] + ["{{" diff "{" emit(x) "[" w - 1 "]}}, " emit(x) " }"] AS-UINT-OP : - ["$unsigned(" emit(args(e)[0]) " "] + ["$unsigned(" emit(args(e)[0]) ")"] AS-SINT-OP : - ["$signed(" emit(args(e)[0]) " "] + ["$signed(" emit(args(e)[0]) ")"] DYN-SHIFT-LEFT-OP : [emit(args(e)[0]) " << " emit(args(e)[1])] DYN-SHIFT-RIGHT-OP : [emit(args(e)[0]) " >> " emit(args(e)[1])] - SHIFT-LEFT-OP : [emit(args(e)[0]) " << " emit(args(e)[1])] - SHIFT-RIGHT-OP : [emit(args(e)[0]) " >> " emit(args(e)[1])] + SHIFT-LEFT-OP : [emit(args(e)[0]) " << " consts(e)[0]] + SHIFT-RIGHT-OP : [emit(args(e)[0]) " >> " consts(e)[0]] NEG-OP : ["-{" emit(args(e)[0]) "}"] CONVERT-OP : match(type(args(e)[0])) : @@ -239,12 +242,15 @@ defn emit-module (m:InModule) : println-all(a) for x in insts do : - println-all([" " value(x) " " key(x) ".clk(clk),"]) + println-all([" " value(x) " " key(x) " ("]) + print(" ") + print-all([".clk( clk )"]) for (y in inst-ports[key(x)],i in 1 to false) do : + print(",\n") print(" ") print-all(y) - if length(inst-ports[key(x)]) != i : - print(",\n") + ;if length(inst-ports[key(x)]) != i : + ;print(",\n") println("\n );") if length(updates) != 0 : diff --git a/test/chisel3/ALUTop.fir b/test/chisel3/ALUTop.fir index b9386349..5ebcbccc 100644 --- a/test/chisel3/ALUTop.fir +++ b/test/chisel3/ALUTop.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit ALUTop : diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir index 2c2ad772..eeed3309 100644 --- a/test/chisel3/BundleWire.fir +++ b/test/chisel3/BundleWire.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit BundleWire : diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir index c1dc41cd..925b8e34 100644 --- a/test/chisel3/ComplexAssign.fir +++ b/test/chisel3/ComplexAssign.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit ComplexAssign : diff --git a/test/chisel3/Control.fir b/test/chisel3/Control.fir index 2d109102..28bb3d87 100644 --- a/test/chisel3/Control.fir +++ b/test/chisel3/Control.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Control : diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir index b81eb7e9..06010573 100644 --- a/test/chisel3/Core.fir +++ b/test/chisel3/Core.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Core : @@ -97,7 +97,7 @@ circuit Core : input waddr : UInt<5> input wdata : UInt<32> - mem regs : UInt<32>[32] + cmem regs : UInt<32>[32] node T_1286 = eq(raddr1, UInt<1>(0)) node T_1287 = bit-not(T_1286) accessor T_1288 = regs[raddr1] diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir index 6f04dfb9..0f80f687 100644 --- a/test/chisel3/Counter.fir +++ b/test/chisel3/Counter.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Counter : diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir index ef62df98..10643549 100644 --- a/test/chisel3/Datapath.fir +++ b/test/chisel3/Datapath.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Datapath : @@ -97,7 +97,7 @@ circuit Datapath : input waddr : UInt<5> input wdata : UInt<32> - mem regs : UInt<32>[32] + cmem regs : UInt<32>[32] node T_495 = eq(raddr1, UInt<1>(0)) node T_496 = bit-not(T_495) accessor T_497 = regs[raddr1] diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir index 795b03e4..bfc8f9c3 100644 --- a/test/chisel3/EnableShiftRegister.fir +++ b/test/chisel3/EnableShiftRegister.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit EnableShiftRegister : diff --git a/test/chisel3/GCD.fir b/test/chisel3/GCD.fir index d6f7d798..90b0a8b8 100644 --- a/test/chisel3/GCD.fir +++ b/test/chisel3/GCD.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit GCD : diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir index cdf1b835..29a2823a 100644 --- a/test/chisel3/LFSR16.fir +++ b/test/chisel3/LFSR16.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit LFSR16 : diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir index 375bfcff..a0cc0b7d 100644 --- a/test/chisel3/MemorySearch.fir +++ b/test/chisel3/MemorySearch.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit MemorySearch : diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir index 87d0fed0..758f544c 100644 --- a/test/chisel3/ModuleVec.fir +++ b/test/chisel3/ModuleVec.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit ModuleVec : diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir index fefe42bd..3be7f928 100644 --- a/test/chisel3/ModuleWire.fir +++ b/test/chisel3/ModuleWire.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit ModuleWire : diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir index fab610b6..c5dccb6f 100644 --- a/test/chisel3/Mul.fir +++ b/test/chisel3/Mul.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Mul : diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir index a7631277..886a01ba 100644 --- a/test/chisel3/Outer.fir +++ b/test/chisel3/Outer.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Outer : diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir index 3a9658eb..3d51ece3 100644 --- a/test/chisel3/RegisterVecShift.fir +++ b/test/chisel3/RegisterVecShift.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit RegisterVecShift : diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir index bd02bac3..425f8a91 100644 --- a/test/chisel3/Risc.fir +++ b/test/chisel3/Risc.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Risc : @@ -10,8 +10,8 @@ circuit Risc : input wrAddr : UInt<8> input wrData : UInt<32> - mem file : UInt<32>[256] - mem code : UInt<32>[256] + cmem file : UInt<32>[256] + cmem code : UInt<32>[256] reg pc : UInt<8> on-reset pc := UInt<8>(0) accessor inst = code[pc] diff --git a/test/chisel3/Rom.fir b/test/chisel3/Rom.fir index 8e80b7d4..1c19d9b3 100644 --- a/test/chisel3/Rom.fir +++ b/test/chisel3/Rom.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Rom : diff --git a/test/chisel3/SIntOps.fir b/test/chisel3/SIntOps.fir index ee1aa366..59ad2a47 100644 --- a/test/chisel3/SIntOps.fir +++ b/test/chisel3/SIntOps.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit SIntOps : @@ -26,15 +26,15 @@ circuit SIntOps : node T_39 = sub-wrap(a, b) subout := T_39 node T_40 = mul(a, b) - node T_41 = bits(T_40, 15, 0) - timesout := T_41 + node T_41 = bits(as-UInt(T_40), 15, 0) + timesout := as-SInt(T_41) node T_42 = mul(a, b) - node T_43 = bits(T_42, 15, 0) - divout := T_43 - modout := UInt<1>(0) + node T_43 = bits(as-UInt(T_42), 15, 0) + divout := as-SInt(T_43) + modout := SInt<1>(0) node T_44 = shl(a, 12) - node T_45 = bits(T_44, 15, 0) - lshiftout := T_45 + node T_45 = bits(as-UInt(T_44), 15, 0) + lshiftout := as-SInt(T_45) node T_46 = shr(a, 8) rshiftout := T_46 node T_47 = lt(a, b) diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir index 84cb6ccd..caa70da5 100644 --- a/test/chisel3/Stack.fir +++ b/test/chisel3/Stack.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Stack : @@ -9,7 +9,7 @@ circuit Stack : output dataOut : UInt<32> input dataIn : UInt<32> - mem stack_mem : UInt<32>[16] + cmem stack_mem : UInt<32>[16] reg sp : UInt<5> on-reset sp := UInt<5>(0) reg out : UInt<32> diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir index d64916f1..e7397f61 100644 --- a/test/chisel3/Tbl.fir +++ b/test/chisel3/Tbl.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Tbl : @@ -8,7 +8,7 @@ circuit Tbl : output o : UInt<16> input we : UInt<1> - mem m : UInt<10>[256] + cmem m : UInt<10>[256] o := UInt<1>(0) when we : accessor T_13 = m[i] diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir index eeec18ee..01d78cd0 100644 --- a/test/chisel3/Tile.fir +++ b/test/chisel3/Tile.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit Tile : @@ -97,7 +97,7 @@ circuit Tile : input waddr : UInt<5> input wdata : UInt<32> - mem regs : UInt<32>[32] + cmem regs : UInt<32>[32] node T_1616 = eq(raddr1, UInt<1>(0)) node T_1617 = bit-not(T_1616) accessor T_1618 = regs[raddr1] @@ -1026,7 +1026,7 @@ circuit Tile : input enq : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}} output deq : {valid : UInt<1>, flip ready : UInt<1>, bits : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}} - mem ram : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}[4] + cmem ram : {mask : UInt<4>, tag : UInt<5>, rw : UInt<1>, addr : UInt<32>}[4] reg T_2381 : UInt<2> on-reset T_2381 := UInt<2>(0) reg T_2382 : UInt<2> @@ -1089,7 +1089,7 @@ circuit Tile : input enq : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}} output deq : {valid : UInt<1>, flip ready : UInt<1>, bits : {data : UInt<32>}} - mem ram : {data : UInt<32>}[4] + cmem ram : {data : UInt<32>}[4] reg T_2412 : UInt<2> on-reset T_2412 := UInt<2>(0) reg T_2413 : UInt<2> diff --git a/test/chisel3/UIntOps.fir b/test/chisel3/UIntOps.fir index 9b219523..1707bbee 100644 --- a/test/chisel3/UIntOps.fir +++ b/test/chisel3/UIntOps.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit UIntOps : diff --git a/test/chisel3/VendingMachine.fir b/test/chisel3/VendingMachine.fir index a1149dbc..39723b05 100644 --- a/test/chisel3/VendingMachine.fir +++ b/test/chisel3/VendingMachine.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit VendingMachine : diff --git a/test/errors/high-form/NegUInt.fir b/test/errors/high-form/NegUInt.fir index 9050ac12..a793cdb9 100644 --- a/test/errors/high-form/NegUInt.fir +++ b/test/errors/high-form/NegUInt.fir @@ -1,5 +1,5 @@ -; to run: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s -; to check: UIntValue cannot be negative. +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; CHECK: UIntValue cannot be negative. circuit Top : module Top : diff --git a/test/features/Long.fir b/test/features/Long.fir new file mode 100644 index 00000000..e03ab091 --- /dev/null +++ b/test/features/Long.fir @@ -0,0 +1,6 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done +circuit Top : + module Top : + wire a : UInt + a := UInt(4261441663) diff --git a/test/riscv-mini/Core.fir b/test/riscv-mini/Core.fir new file mode 100644 index 00000000..06010573 --- /dev/null +++ b/test/riscv-mini/Core.fir @@ -0,0 +1,1023 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +;CHECK: Done! + +circuit Core : + module ALU : + input B : UInt<32> + output out : UInt<32> + output sum : UInt<32> + input A : UInt<32> + input alu_op : UInt<4> + + node shamt = bits(B, 4, 0) + node T_1224 = add-wrap(A, B) + node T_1225 = sub-wrap(A, B) + node T_1226 = convert(A) + node T_1227 = dshr(T_1226, shamt) + node T_1228 = as-UInt(T_1227) + node T_1229 = dshr(A, shamt) + node T_1230 = dshl(A, shamt) + node T_1231 = bits(T_1230, 31, 0) + node T_1232 = convert(A) + node T_1233 = convert(B) + node T_1234 = lt(T_1232, T_1233) + node T_1235 = as-UInt(T_1234) + node T_1236 = lt(A, B) + node T_1237 = as-UInt(T_1236) + node T_1238 = bit-and(A, B) + node T_1239 = bit-or(A, B) + node T_1240 = bit-xor(A, B) + node T_1241 = eq(UInt<4>(10), alu_op) + node T_1242 = mux(T_1241, A, B) + node T_1243 = eq(UInt<4>(4), alu_op) + node T_1244 = mux(T_1243, T_1240, T_1242) + node T_1245 = eq(UInt<4>(3), alu_op) + node T_1246 = mux(T_1245, T_1239, T_1244) + node T_1247 = eq(UInt<4>(2), alu_op) + node T_1248 = mux(T_1247, T_1238, T_1246) + node T_1249 = eq(UInt<4>(7), alu_op) + node T_1250 = mux(T_1249, T_1237, T_1248) + node T_1251 = eq(UInt<4>(5), alu_op) + node T_1252 = mux(T_1251, T_1235, T_1250) + node T_1253 = eq(UInt<4>(6), alu_op) + node T_1254 = mux(T_1253, T_1231, T_1252) + node T_1255 = eq(UInt<4>(8), alu_op) + node T_1256 = mux(T_1255, T_1229, T_1254) + node T_1257 = eq(UInt<4>(9), alu_op) + node T_1258 = mux(T_1257, T_1228, T_1256) + node T_1259 = eq(UInt<4>(1), alu_op) + node T_1260 = mux(T_1259, T_1225, T_1258) + node T_1261 = eq(UInt<4>(0), alu_op) + node oot = mux(T_1261, T_1224, T_1260) + node T_1262 = bits(oot, 31, 0) + out := T_1262 + node T_1263 = bit(alu_op, 0) + node T_1264 = sub-wrap(UInt<1>(0), B) + node T_1265 = mux(T_1263, T_1264, B) + node T_1266 = add-wrap(A, T_1265) + sum := T_1266 + module BrCond : + input br_type : UInt<3> + input rs1 : UInt<32> + input rs2 : UInt<32> + output taken : UInt<1> + + node eq = eq(rs1, rs2) + node neq = bit-not(eq) + node T_1267 = convert(rs1) + node T_1268 = convert(rs2) + node lt = lt(T_1267, T_1268) + node ge = bit-not(lt) + node ltu = lt(rs1, rs2) + node geu = bit-not(ltu) + node T_1269 = eq(br_type, UInt<3>(2)) + node T_1270 = bit-and(T_1269, eq) + node T_1271 = eq(br_type, UInt<3>(6)) + node T_1272 = bit-and(T_1271, neq) + node T_1273 = bit-or(T_1270, T_1272) + node T_1274 = eq(br_type, UInt<3>(1)) + node T_1275 = bit-and(T_1274, lt) + node T_1276 = bit-or(T_1273, T_1275) + node T_1277 = eq(br_type, UInt<3>(5)) + node T_1278 = bit-and(T_1277, ge) + node T_1279 = bit-or(T_1276, T_1278) + node T_1280 = eq(br_type, UInt<3>(0)) + node T_1281 = bit-and(T_1280, ltu) + node T_1282 = bit-or(T_1279, T_1281) + node T_1283 = eq(br_type, UInt<3>(4)) + node T_1284 = bit-and(T_1283, geu) + node T_1285 = bit-or(T_1282, T_1284) + taken := T_1285 + module RegFile : + input raddr1 : UInt<5> + input raddr2 : UInt<5> + output rdata1 : UInt<32> + output rdata2 : UInt<32> + input wen : UInt<1> + input waddr : UInt<5> + input wdata : UInt<32> + + cmem regs : UInt<32>[32] + node T_1286 = eq(raddr1, UInt<1>(0)) + node T_1287 = bit-not(T_1286) + accessor T_1288 = regs[raddr1] + node T_1289 = mux(T_1287, T_1288, UInt<1>(0)) + rdata1 := T_1289 + node T_1290 = eq(raddr2, UInt<1>(0)) + node T_1291 = bit-not(T_1290) + accessor T_1292 = regs[raddr2] + node T_1293 = mux(T_1291, T_1292, UInt<1>(0)) + rdata2 := T_1293 + node T_1294 = eq(waddr, UInt<1>(0)) + node T_1295 = bit-not(T_1294) + node T_1296 = bit-and(wen, T_1295) + when T_1296 : + accessor T_1297 = regs[waddr] + T_1297 := wdata + module ImmGenWire : + output out : UInt<32> + input sel : UInt<3> + input inst : UInt<32> + + node T_1298 = bits(inst, 31, 20) + node Iimm = convert(T_1298) + node T_1299 = bits(inst, 31, 25) + node T_1300 = bits(inst, 11, 7) + node T_1301 = cat(T_1299, T_1300) + node Simm = convert(T_1301) + node T_1302 = bit(inst, 31) + node T_1303 = bit(inst, 7) + node T_1304 = bits(inst, 30, 25) + node T_1305 = bits(inst, 11, 8) + node T_1306 = cat(T_1302, T_1303) + node T_1307 = cat(T_1305, UInt<1>(0)) + node T_1308 = cat(T_1304, T_1307) + node T_1309 = cat(T_1306, T_1308) + node Bimm = convert(T_1309) + node T_1310 = bits(inst, 31, 12) + node T_1311 = cat(T_1310, UInt<12>(0)) + node Uimm = convert(T_1311) + node T_1312 = bit(inst, 31) + node T_1313 = bits(inst, 19, 12) + node T_1314 = bit(inst, 20) + node T_1315 = bits(inst, 30, 25) + node T_1316 = bits(inst, 24, 21) + node T_1317 = cat(T_1313, T_1314) + node T_1318 = cat(T_1312, T_1317) + node T_1319 = cat(T_1316, UInt<1>(0)) + node T_1320 = cat(T_1315, T_1319) + node T_1321 = cat(T_1318, T_1320) + node Jimm = convert(T_1321) + node T_1322 = bits(inst, 19, 15) + node T_1323 = pad(T_1322, 32) + node Zimm = convert(T_1323) + node T_1324 = eq(UInt<3>(3), sel) + node T_1325 = mux(T_1324, Jimm, Zimm) + node T_1326 = eq(UInt<3>(2), sel) + node T_1327 = mux(T_1326, Uimm, T_1325) + node T_1328 = eq(UInt<3>(4), sel) + node T_1329 = mux(T_1328, Bimm, T_1327) + node T_1330 = eq(UInt<3>(1), sel) + node T_1331 = mux(T_1330, Simm, T_1329) + node T_1332 = eq(UInt<3>(0), sel) + node T_1333 = mux(T_1332, Iimm, T_1331) + node T_1334 = as-UInt(T_1333) + out := T_1334 + module CSR : + output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>} + input src : UInt<32> + input cmd : UInt<2> + output data : UInt<32> + input addr : UInt<12> + + reg reg_tohost : UInt<32> + on-reset reg_tohost := UInt<32>(0) + reg reg_status : UInt<32> + on-reset reg_status := UInt<32>(0) + host.tohost := reg_tohost + host.status := reg_status + node T_1335 = eq(UInt<12>(1291), addr) + node T_1336 = mux(T_1335, host.hid, UInt<1>(0)) + node T_1337 = eq(UInt<12>(1290), addr) + node T_1338 = mux(T_1337, reg_status, T_1336) + node T_1339 = eq(UInt<12>(1310), addr) + node T_1340 = mux(T_1339, reg_tohost, T_1338) + data := T_1340 + node T_1341 = eq(cmd, UInt<2>(1)) + when T_1341 : + node T_1342 = eq(addr, UInt<12>(1310)) + when T_1342 : reg_tohost := src + node T_1343 = eq(addr, UInt<12>(1290)) + when T_1343 : reg_status := src + node T_1344 = eq(cmd, UInt<2>(2)) + node T_1345 = neq(src, UInt<1>(0)) + node T_1346 = bit-and(T_1344, T_1345) + when T_1346 : + node T_1347 = eq(addr, UInt<12>(1310)) + when T_1347 : + node T_1348 = dshl(UInt<1>(1), src) + node T_1349 = bit-or(data, T_1348) + reg_tohost := T_1349 + node T_1350 = eq(addr, UInt<12>(1290)) + when T_1350 : + node T_1351 = dshl(UInt<1>(1), src) + node T_1352 = bit-or(data, T_1351) + reg_status := T_1352 + node T_1353 = eq(cmd, UInt<2>(3)) + node T_1354 = neq(src, UInt<1>(0)) + node T_1355 = bit-and(T_1353, T_1354) + when T_1355 : + node T_1356 = eq(addr, UInt<12>(1310)) + when T_1356 : + node T_1357 = dshl(UInt<1>(0), src) + node T_1358 = bit-and(data, T_1357) + reg_tohost := T_1358 + node T_1359 = eq(addr, UInt<12>(1290)) + when T_1359 : + node T_1360 = dshl(UInt<1>(0), src) + node T_1361 = bit-and(data, T_1360) + reg_status := T_1361 + module Datapath : + output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>} + input ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>} + output icache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} + output dcache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} + input stall : UInt<1> + + inst alu of ALU + inst brCond of BrCond + inst regFile of RegFile + inst immGen of ImmGenWire + reg fe_inst : UInt<32> + on-reset fe_inst := UInt<32>(0) + reg fe_pc : UInt + reg ew_inst : UInt<32> + on-reset ew_inst := UInt<32>(0) + reg ew_pc : UInt + reg ew_alu : UInt + node T_1362 = sub-wrap(UInt<14>(8192), UInt<32>(4)) + reg pc : UInt<32> + on-reset pc := T_1362 + node T_1363 = eq(ctrl.pc_sel, UInt<1>(1)) + node T_1364 = bit-or(T_1363, brCond.taken) + node T_1365 = add-wrap(pc, UInt<3>(4)) + node iaddr = mux(T_1364, alu.sum, T_1365) + node T_1366 = eq(ctrl.inst_type, UInt<1>(1)) + node T_1367 = bit-or(T_1366, brCond.taken) + node inst = mux(T_1367, UInt<32>(19), icache.dout) + icache.we := UInt<1>(0) + icache.din := UInt<1>(0) + icache.addr := iaddr + icache.re := ctrl.inst_re + node T_1368 = eq(dcache.we, UInt<1>(0)) + node T_1369 = bit-not(T_1368) + node T_1370 = bit-not(T_1369) + node T_1371 = bit-and(icache.re, T_1370) + node T_1372 = mux(T_1371, iaddr, pc) + pc := T_1372 + node T_1373 = bit-not(stall) + when T_1373 : + fe_pc := pc + fe_inst := inst + ctrl.inst := fe_inst + ctrl.stall := stall + node rd_addr = bits(fe_inst, 11, 7) + node rs1_addr = bits(fe_inst, 19, 15) + node rs2_addr = bits(fe_inst, 24, 20) + regFile.raddr1 := rs1_addr + regFile.raddr2 := rs2_addr + immGen.inst := fe_inst + immGen.sel := ctrl.imm_sel + node T_1374 = eq(rs1_addr, UInt<1>(0)) + node rs1NotZero = bit-not(T_1374) + node T_1375 = eq(rs2_addr, UInt<1>(0)) + node rs2NotZero = bit-not(T_1375) + node T_1376 = eq(ctrl.wb_sel, UInt<2>(0)) + node alutype = bit-and(ctrl.wb_en, T_1376) + node ex_rd_addr = bits(ew_inst, 11, 7) + node T_1377 = bit-and(alutype, rs1NotZero) + node T_1378 = eq(rs1_addr, ex_rd_addr) + node T_1379 = bit-and(T_1377, T_1378) + node rs1 = mux(T_1379, ew_alu, regFile.rdata1) + node T_1380 = bit-and(alutype, rs2NotZero) + node T_1381 = eq(rs2_addr, ex_rd_addr) + node T_1382 = bit-and(T_1380, T_1381) + node rs2 = mux(T_1382, ew_alu, regFile.rdata2) + node T_1383 = eq(ctrl.A_sel, UInt<1>(0)) + node T_1384 = mux(T_1383, rs1, fe_pc) + alu.A := T_1384 + node T_1385 = eq(ctrl.B_sel, UInt<1>(0)) + node T_1386 = mux(T_1385, rs2, immGen.out) + alu.B := T_1386 + alu.alu_op := ctrl.alu_op + brCond.rs1 := rs1 + brCond.rs2 := rs2 + brCond.br_type := ctrl.br_type + node T_1387 = bit(alu.sum, 1) + node T_1388 = dshl(T_1387, UInt<3>(4)) + node T_1389 = bit(alu.sum, 0) + node T_1390 = dshl(T_1389, UInt<2>(3)) + node woffset = bit-or(T_1388, T_1390) + dcache.re := ctrl.data_re + node T_1391 = mux(stall, ew_alu, alu.sum) + dcache.addr := T_1391 + node T_1392 = bits(alu.sum, 1, 0) + node T_1393 = dshl(UInt<2>(3), T_1392) + node T_1394 = bits(T_1393, 3, 0) + node T_1395 = bits(alu.sum, 1, 0) + node T_1396 = dshl(UInt<1>(1), T_1395) + node T_1397 = bits(T_1396, 3, 0) + node T_1398 = eq(UInt<2>(2), ctrl.st_type) + node T_1399 = mux(T_1398, T_1397, UInt<4>(0)) + node T_1400 = eq(UInt<2>(1), ctrl.st_type) + node T_1401 = mux(T_1400, T_1394, T_1399) + node T_1402 = eq(UInt<2>(0), ctrl.st_type) + node T_1403 = mux(T_1402, UInt<4>(15), T_1401) + node T_1404 = mux(stall, UInt<4>(0), T_1403) + dcache.we := T_1404 + node T_1405 = dshl(rs2, woffset) + node T_1406 = bits(T_1405, 31, 0) + dcache.din := T_1406 + node T_1407 = bit-not(stall) + when T_1407 : + ew_pc := fe_pc + ew_inst := fe_inst + ew_alu := alu.out + node T_1408 = bit(ew_alu, 1) + node T_1409 = dshl(T_1408, UInt<3>(4)) + node T_1410 = bit(ew_alu, 0) + node T_1411 = dshl(T_1410, UInt<2>(3)) + node loffset = bit-or(T_1409, T_1411) + node lshift = dshr(dcache.dout, loffset) + node T_1412 = bits(lshift, 15, 0) + node T_1413 = convert(T_1412) + node T_1414 = pad(T_1413, 32) + node T_1415 = as-UInt(T_1414) + node T_1416 = bits(lshift, 7, 0) + node T_1417 = convert(T_1416) + node T_1418 = pad(T_1417, 32) + node T_1419 = as-UInt(T_1418) + node T_1420 = bits(lshift, 15, 0) + node T_1421 = bits(lshift, 7, 0) + node T_1422 = eq(UInt<3>(4), ctrl.ld_type) + node T_1423 = mux(T_1422, T_1421, dcache.dout) + node T_1424 = eq(UInt<3>(3), ctrl.ld_type) + node T_1425 = mux(T_1424, T_1420, T_1423) + node T_1426 = eq(UInt<3>(2), ctrl.ld_type) + node T_1427 = mux(T_1426, T_1419, T_1425) + node T_1428 = eq(UInt<3>(1), ctrl.ld_type) + node load = mux(T_1428, T_1415, T_1427) + inst csr of CSR + host := csr.host + csr.src := ew_alu + node T_1429 = bits(ew_inst, 31, 20) + csr.addr := T_1429 + csr.cmd := ctrl.csr_cmd + node T_1430 = add-wrap(ew_pc, UInt<3>(4)) + node T_1431 = eq(UInt<2>(3), ctrl.wb_sel) + node T_1432 = mux(T_1431, csr.data, ew_alu) + node T_1433 = eq(UInt<2>(2), ctrl.wb_sel) + node T_1434 = mux(T_1433, T_1430, T_1432) + node T_1435 = eq(UInt<2>(1), ctrl.wb_sel) + node regWrite = mux(T_1435, load, T_1434) + regFile.wen := ctrl.wb_en + regFile.waddr := ex_rd_addr + regFile.wdata := regWrite + module Control : + output ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>} + + node T_1436 = bit-and(UInt<7>(127), ctrl.inst) + node T_1437 = eq(T_1436, UInt<6>(55)) + node T_1438 = bit-and(UInt<7>(127), ctrl.inst) + node T_1439 = eq(T_1438, UInt<5>(23)) + node T_1440 = bit-and(UInt<7>(127), ctrl.inst) + node T_1441 = eq(T_1440, UInt<7>(111)) + node T_1442 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1443 = eq(T_1442, UInt<7>(103)) + node T_1444 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1445 = eq(T_1444, UInt<7>(99)) + node T_1446 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1447 = eq(T_1446, UInt<13>(4195)) + node T_1448 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1449 = eq(T_1448, UInt<15>(16483)) + node T_1450 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1451 = eq(T_1450, UInt<15>(20579)) + node T_1452 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1453 = eq(T_1452, UInt<15>(24675)) + node T_1454 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1455 = eq(T_1454, UInt<15>(28771)) + node T_1456 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1457 = eq(T_1456, UInt<2>(3)) + node T_1458 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1459 = eq(T_1458, UInt<13>(4099)) + node T_1460 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1461 = eq(T_1460, UInt<14>(8195)) + node T_1462 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1463 = eq(T_1462, UInt<15>(16387)) + node T_1464 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1465 = eq(T_1464, UInt<15>(20483)) + node T_1466 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1467 = eq(T_1466, UInt<6>(35)) + node T_1468 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1469 = eq(T_1468, UInt<13>(4131)) + node T_1470 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1471 = eq(T_1470, UInt<14>(8227)) + node T_1472 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1473 = eq(T_1472, UInt<5>(19)) + node T_1474 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1475 = eq(T_1474, UInt<14>(8211)) + node T_1476 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1477 = eq(T_1476, UInt<14>(12307)) + node T_1478 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1479 = eq(T_1478, UInt<15>(16403)) + node T_1480 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1481 = eq(T_1480, UInt<15>(24595)) + node T_1482 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1483 = eq(T_1482, UInt<15>(28691)) + node T_1484 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1485 = eq(T_1484, UInt<13>(4115)) + node T_1486 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1487 = eq(T_1486, UInt<15>(20499)) + node T_1488 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1489 = eq(T_1488, UInt<31>(1073762323)) + node T_1490 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1491 = eq(T_1490, UInt<6>(51)) + node T_1492 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1493 = eq(T_1492, UInt<31>(1073741875)) + node T_1494 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1495 = eq(T_1494, UInt<13>(4147)) + node T_1496 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1497 = eq(T_1496, UInt<14>(8243)) + node T_1498 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1499 = eq(T_1498, UInt<14>(12339)) + node T_1500 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1501 = eq(T_1500, UInt<15>(16435)) + node T_1502 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1503 = eq(T_1502, UInt<15>(20531)) + node T_1504 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1505 = eq(T_1504, UInt<31>(1073762355)) + node T_1506 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1507 = eq(T_1506, UInt<15>(24627)) + node T_1508 = bit-and(UInt<32>(4261441663), ctrl.inst) + node T_1509 = eq(T_1508, UInt<15>(28723)) + node T_1510 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1511 = eq(T_1510, UInt<13>(4211)) + node T_1512 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1513 = eq(T_1512, UInt<14>(8307)) + node T_1514 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1515 = eq(T_1514, UInt<14>(12403)) + node T_1516 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1517 = eq(T_1516, UInt<15>(20595)) + node T_1518 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1519 = eq(T_1518, UInt<15>(24691)) + node T_1520 = bit-and(UInt<15>(28799), ctrl.inst) + node T_1521 = eq(T_1520, UInt<15>(28787)) + node T_1522 = mux(T_1521, UInt<1>(0), UInt<1>(0)) + node T_1523 = mux(T_1519, UInt<1>(0), T_1522) + node T_1524 = mux(T_1517, UInt<1>(0), T_1523) + node T_1525 = mux(T_1515, UInt<1>(0), T_1524) + node T_1526 = mux(T_1513, UInt<1>(0), T_1525) + node T_1527 = mux(T_1511, UInt<1>(0), T_1526) + node T_1528 = mux(T_1509, UInt<1>(0), T_1527) + node T_1529 = mux(T_1507, UInt<1>(0), T_1528) + node T_1530 = mux(T_1505, UInt<1>(0), T_1529) + node T_1531 = mux(T_1503, UInt<1>(0), T_1530) + node T_1532 = mux(T_1501, UInt<1>(0), T_1531) + node T_1533 = mux(T_1499, UInt<1>(0), T_1532) + node T_1534 = mux(T_1497, UInt<1>(0), T_1533) + node T_1535 = mux(T_1495, UInt<1>(0), T_1534) + node T_1536 = mux(T_1493, UInt<1>(0), T_1535) + node T_1537 = mux(T_1491, UInt<1>(0), T_1536) + node T_1538 = mux(T_1489, UInt<1>(0), T_1537) + node T_1539 = mux(T_1487, UInt<1>(0), T_1538) + node T_1540 = mux(T_1485, UInt<1>(0), T_1539) + node T_1541 = mux(T_1483, UInt<1>(0), T_1540) + node T_1542 = mux(T_1481, UInt<1>(0), T_1541) + node T_1543 = mux(T_1479, UInt<1>(0), T_1542) + node T_1544 = mux(T_1477, UInt<1>(0), T_1543) + node T_1545 = mux(T_1475, UInt<1>(0), T_1544) + node T_1546 = mux(T_1473, UInt<1>(0), T_1545) + node T_1547 = mux(T_1471, UInt<1>(0), T_1546) + node T_1548 = mux(T_1469, UInt<1>(0), T_1547) + node T_1549 = mux(T_1467, UInt<1>(0), T_1548) + node T_1550 = mux(T_1465, UInt<1>(0), T_1549) + node T_1551 = mux(T_1463, UInt<1>(0), T_1550) + node T_1552 = mux(T_1461, UInt<1>(0), T_1551) + node T_1553 = mux(T_1459, UInt<1>(0), T_1552) + node T_1554 = mux(T_1457, UInt<1>(0), T_1553) + node T_1555 = mux(T_1455, UInt<1>(0), T_1554) + node T_1556 = mux(T_1453, UInt<1>(0), T_1555) + node T_1557 = mux(T_1451, UInt<1>(0), T_1556) + node T_1558 = mux(T_1449, UInt<1>(0), T_1557) + node T_1559 = mux(T_1447, UInt<1>(0), T_1558) + node T_1560 = mux(T_1445, UInt<1>(0), T_1559) + node T_1561 = mux(T_1443, UInt<1>(1), T_1560) + node T_1562 = mux(T_1441, UInt<1>(1), T_1561) + node T_1563 = mux(T_1439, UInt<1>(0), T_1562) + node T_1564 = mux(T_1437, UInt<1>(0), T_1563) + node T_1565 = mux(T_1521, UInt<1>(1), UInt<1>(1)) + node T_1566 = mux(T_1519, UInt<1>(1), T_1565) + node T_1567 = mux(T_1517, UInt<1>(1), T_1566) + node T_1568 = mux(T_1515, UInt<1>(0), T_1567) + node T_1569 = mux(T_1513, UInt<1>(0), T_1568) + node T_1570 = mux(T_1511, UInt<1>(0), T_1569) + node T_1571 = mux(T_1509, UInt<1>(0), T_1570) + node T_1572 = mux(T_1507, UInt<1>(0), T_1571) + node T_1573 = mux(T_1505, UInt<1>(0), T_1572) + node T_1574 = mux(T_1503, UInt<1>(0), T_1573) + node T_1575 = mux(T_1501, UInt<1>(0), T_1574) + node T_1576 = mux(T_1499, UInt<1>(0), T_1575) + node T_1577 = mux(T_1497, UInt<1>(0), T_1576) + node T_1578 = mux(T_1495, UInt<1>(0), T_1577) + node T_1579 = mux(T_1493, UInt<1>(0), T_1578) + node T_1580 = mux(T_1491, UInt<1>(0), T_1579) + node T_1581 = mux(T_1489, UInt<1>(0), T_1580) + node T_1582 = mux(T_1487, UInt<1>(0), T_1581) + node T_1583 = mux(T_1485, UInt<1>(0), T_1582) + node T_1584 = mux(T_1483, UInt<1>(0), T_1583) + node T_1585 = mux(T_1481, UInt<1>(0), T_1584) + node T_1586 = mux(T_1479, UInt<1>(0), T_1585) + node T_1587 = mux(T_1477, UInt<1>(0), T_1586) + node T_1588 = mux(T_1475, UInt<1>(0), T_1587) + node T_1589 = mux(T_1473, UInt<1>(0), T_1588) + node T_1590 = mux(T_1471, UInt<1>(0), T_1589) + node T_1591 = mux(T_1469, UInt<1>(0), T_1590) + node T_1592 = mux(T_1467, UInt<1>(0), T_1591) + node T_1593 = mux(T_1465, UInt<1>(0), T_1592) + node T_1594 = mux(T_1463, UInt<1>(0), T_1593) + node T_1595 = mux(T_1461, UInt<1>(0), T_1594) + node T_1596 = mux(T_1459, UInt<1>(0), T_1595) + node T_1597 = mux(T_1457, UInt<1>(0), T_1596) + node T_1598 = mux(T_1455, UInt<1>(1), T_1597) + node T_1599 = mux(T_1453, UInt<1>(1), T_1598) + node T_1600 = mux(T_1451, UInt<1>(1), T_1599) + node T_1601 = mux(T_1449, UInt<1>(1), T_1600) + node T_1602 = mux(T_1447, UInt<1>(1), T_1601) + node T_1603 = mux(T_1445, UInt<1>(1), T_1602) + node T_1604 = mux(T_1443, UInt<1>(0), T_1603) + node T_1605 = mux(T_1441, UInt<1>(1), T_1604) + node T_1606 = mux(T_1439, UInt<1>(1), T_1605) + node T_1607 = mux(T_1437, UInt<1>(1), T_1606) + node T_1608 = mux(T_1521, UInt<1>(1), UInt<1>(0)) + node T_1609 = mux(T_1519, UInt<1>(1), T_1608) + node T_1610 = mux(T_1517, UInt<1>(1), T_1609) + node T_1611 = mux(T_1515, UInt<1>(0), T_1610) + node T_1612 = mux(T_1513, UInt<1>(0), T_1611) + node T_1613 = mux(T_1511, UInt<1>(0), T_1612) + node T_1614 = mux(T_1509, UInt<1>(0), T_1613) + node T_1615 = mux(T_1507, UInt<1>(0), T_1614) + node T_1616 = mux(T_1505, UInt<1>(0), T_1615) + node T_1617 = mux(T_1503, UInt<1>(0), T_1616) + node T_1618 = mux(T_1501, UInt<1>(0), T_1617) + node T_1619 = mux(T_1499, UInt<1>(0), T_1618) + node T_1620 = mux(T_1497, UInt<1>(0), T_1619) + node T_1621 = mux(T_1495, UInt<1>(0), T_1620) + node T_1622 = mux(T_1493, UInt<1>(0), T_1621) + node T_1623 = mux(T_1491, UInt<1>(0), T_1622) + node T_1624 = mux(T_1489, UInt<1>(1), T_1623) + node T_1625 = mux(T_1487, UInt<1>(1), T_1624) + node T_1626 = mux(T_1485, UInt<1>(1), T_1625) + node T_1627 = mux(T_1483, UInt<1>(1), T_1626) + node T_1628 = mux(T_1481, UInt<1>(1), T_1627) + node T_1629 = mux(T_1479, UInt<1>(1), T_1628) + node T_1630 = mux(T_1477, UInt<1>(1), T_1629) + node T_1631 = mux(T_1475, UInt<1>(1), T_1630) + node T_1632 = mux(T_1473, UInt<1>(1), T_1631) + node T_1633 = mux(T_1471, UInt<1>(1), T_1632) + node T_1634 = mux(T_1469, UInt<1>(1), T_1633) + node T_1635 = mux(T_1467, UInt<1>(1), T_1634) + node T_1636 = mux(T_1465, UInt<1>(1), T_1635) + node T_1637 = mux(T_1463, UInt<1>(1), T_1636) + node T_1638 = mux(T_1461, UInt<1>(1), T_1637) + node T_1639 = mux(T_1459, UInt<1>(1), T_1638) + node T_1640 = mux(T_1457, UInt<1>(1), T_1639) + node T_1641 = mux(T_1455, UInt<1>(1), T_1640) + node T_1642 = mux(T_1453, UInt<1>(1), T_1641) + node T_1643 = mux(T_1451, UInt<1>(1), T_1642) + node T_1644 = mux(T_1449, UInt<1>(1), T_1643) + node T_1645 = mux(T_1447, UInt<1>(1), T_1644) + node T_1646 = mux(T_1445, UInt<1>(1), T_1645) + node T_1647 = mux(T_1443, UInt<1>(1), T_1646) + node T_1648 = mux(T_1441, UInt<1>(1), T_1647) + node T_1649 = mux(T_1439, UInt<1>(1), T_1648) + node T_1650 = mux(T_1437, UInt<1>(1), T_1649) + node T_1651 = mux(T_1521, UInt<3>(5), UInt<3>(7)) + node T_1652 = mux(T_1519, UInt<3>(5), T_1651) + node T_1653 = mux(T_1517, UInt<3>(5), T_1652) + node T_1654 = mux(T_1515, UInt<3>(5), T_1653) + node T_1655 = mux(T_1513, UInt<3>(5), T_1654) + node T_1656 = mux(T_1511, UInt<3>(5), T_1655) + node T_1657 = mux(T_1509, UInt<3>(7), T_1656) + node T_1658 = mux(T_1507, UInt<3>(7), T_1657) + node T_1659 = mux(T_1505, UInt<3>(7), T_1658) + node T_1660 = mux(T_1503, UInt<3>(7), T_1659) + node T_1661 = mux(T_1501, UInt<3>(7), T_1660) + node T_1662 = mux(T_1499, UInt<3>(7), T_1661) + node T_1663 = mux(T_1497, UInt<3>(7), T_1662) + node T_1664 = mux(T_1495, UInt<3>(7), T_1663) + node T_1665 = mux(T_1493, UInt<3>(7), T_1664) + node T_1666 = mux(T_1491, UInt<3>(7), T_1665) + node T_1667 = mux(T_1489, UInt<3>(0), T_1666) + node T_1668 = mux(T_1487, UInt<3>(0), T_1667) + node T_1669 = mux(T_1485, UInt<3>(0), T_1668) + node T_1670 = mux(T_1483, UInt<3>(0), T_1669) + node T_1671 = mux(T_1481, UInt<3>(0), T_1670) + node T_1672 = mux(T_1479, UInt<3>(0), T_1671) + node T_1673 = mux(T_1477, UInt<3>(0), T_1672) + node T_1674 = mux(T_1475, UInt<3>(0), T_1673) + node T_1675 = mux(T_1473, UInt<3>(0), T_1674) + node T_1676 = mux(T_1471, UInt<3>(1), T_1675) + node T_1677 = mux(T_1469, UInt<3>(1), T_1676) + node T_1678 = mux(T_1467, UInt<3>(1), T_1677) + node T_1679 = mux(T_1465, UInt<3>(0), T_1678) + node T_1680 = mux(T_1463, UInt<3>(0), T_1679) + node T_1681 = mux(T_1461, UInt<3>(0), T_1680) + node T_1682 = mux(T_1459, UInt<3>(0), T_1681) + node T_1683 = mux(T_1457, UInt<3>(0), T_1682) + node T_1684 = mux(T_1455, UInt<3>(4), T_1683) + node T_1685 = mux(T_1453, UInt<3>(4), T_1684) + node T_1686 = mux(T_1451, UInt<3>(4), T_1685) + node T_1687 = mux(T_1449, UInt<3>(4), T_1686) + node T_1688 = mux(T_1447, UInt<3>(4), T_1687) + node T_1689 = mux(T_1445, UInt<3>(4), T_1688) + node T_1690 = mux(T_1443, UInt<3>(0), T_1689) + node T_1691 = mux(T_1441, UInt<3>(3), T_1690) + node T_1692 = mux(T_1439, UInt<3>(2), T_1691) + node T_1693 = mux(T_1437, UInt<3>(2), T_1692) + node T_1694 = mux(T_1521, UInt<4>(11), UInt<4>(15)) + node T_1695 = mux(T_1519, UInt<4>(11), T_1694) + node T_1696 = mux(T_1517, UInt<4>(11), T_1695) + node T_1697 = mux(T_1515, UInt<4>(10), T_1696) + node T_1698 = mux(T_1513, UInt<4>(10), T_1697) + node T_1699 = mux(T_1511, UInt<4>(10), T_1698) + node T_1700 = mux(T_1509, UInt<4>(2), T_1699) + node T_1701 = mux(T_1507, UInt<4>(3), T_1700) + node T_1702 = mux(T_1505, UInt<4>(9), T_1701) + node T_1703 = mux(T_1503, UInt<4>(8), T_1702) + node T_1704 = mux(T_1501, UInt<4>(4), T_1703) + node T_1705 = mux(T_1499, UInt<4>(7), T_1704) + node T_1706 = mux(T_1497, UInt<4>(5), T_1705) + node T_1707 = mux(T_1495, UInt<4>(6), T_1706) + node T_1708 = mux(T_1493, UInt<4>(1), T_1707) + node T_1709 = mux(T_1491, UInt<4>(0), T_1708) + node T_1710 = mux(T_1489, UInt<4>(9), T_1709) + node T_1711 = mux(T_1487, UInt<4>(8), T_1710) + node T_1712 = mux(T_1485, UInt<4>(6), T_1711) + node T_1713 = mux(T_1483, UInt<4>(2), T_1712) + node T_1714 = mux(T_1481, UInt<4>(3), T_1713) + node T_1715 = mux(T_1479, UInt<4>(4), T_1714) + node T_1716 = mux(T_1477, UInt<4>(7), T_1715) + node T_1717 = mux(T_1475, UInt<4>(5), T_1716) + node T_1718 = mux(T_1473, UInt<4>(0), T_1717) + node T_1719 = mux(T_1471, UInt<4>(0), T_1718) + node T_1720 = mux(T_1469, UInt<4>(0), T_1719) + node T_1721 = mux(T_1467, UInt<4>(0), T_1720) + node T_1722 = mux(T_1465, UInt<4>(0), T_1721) + node T_1723 = mux(T_1463, UInt<4>(0), T_1722) + node T_1724 = mux(T_1461, UInt<4>(0), T_1723) + node T_1725 = mux(T_1459, UInt<4>(0), T_1724) + node T_1726 = mux(T_1457, UInt<4>(0), T_1725) + node T_1727 = mux(T_1455, UInt<4>(0), T_1726) + node T_1728 = mux(T_1453, UInt<4>(0), T_1727) + node T_1729 = mux(T_1451, UInt<4>(0), T_1728) + node T_1730 = mux(T_1449, UInt<4>(0), T_1729) + node T_1731 = mux(T_1447, UInt<4>(0), T_1730) + node T_1732 = mux(T_1445, UInt<4>(0), T_1731) + node T_1733 = mux(T_1443, UInt<4>(0), T_1732) + node T_1734 = mux(T_1441, UInt<4>(0), T_1733) + node T_1735 = mux(T_1439, UInt<4>(0), T_1734) + node T_1736 = mux(T_1437, UInt<4>(11), T_1735) + node T_1737 = mux(T_1521, UInt<3>(7), UInt<3>(7)) + node T_1738 = mux(T_1519, UInt<3>(7), T_1737) + node T_1739 = mux(T_1517, UInt<3>(7), T_1738) + node T_1740 = mux(T_1515, UInt<3>(7), T_1739) + node T_1741 = mux(T_1513, UInt<3>(7), T_1740) + node T_1742 = mux(T_1511, UInt<3>(7), T_1741) + node T_1743 = mux(T_1509, UInt<3>(7), T_1742) + node T_1744 = mux(T_1507, UInt<3>(7), T_1743) + node T_1745 = mux(T_1505, UInt<3>(7), T_1744) + node T_1746 = mux(T_1503, UInt<3>(7), T_1745) + node T_1747 = mux(T_1501, UInt<3>(7), T_1746) + node T_1748 = mux(T_1499, UInt<3>(7), T_1747) + node T_1749 = mux(T_1497, UInt<3>(7), T_1748) + node T_1750 = mux(T_1495, UInt<3>(7), T_1749) + node T_1751 = mux(T_1493, UInt<3>(7), T_1750) + node T_1752 = mux(T_1491, UInt<3>(7), T_1751) + node T_1753 = mux(T_1489, UInt<3>(7), T_1752) + node T_1754 = mux(T_1487, UInt<3>(7), T_1753) + node T_1755 = mux(T_1485, UInt<3>(7), T_1754) + node T_1756 = mux(T_1483, UInt<3>(7), T_1755) + node T_1757 = mux(T_1481, UInt<3>(7), T_1756) + node T_1758 = mux(T_1479, UInt<3>(7), T_1757) + node T_1759 = mux(T_1477, UInt<3>(7), T_1758) + node T_1760 = mux(T_1475, UInt<3>(7), T_1759) + node T_1761 = mux(T_1473, UInt<3>(7), T_1760) + node T_1762 = mux(T_1471, UInt<3>(7), T_1761) + node T_1763 = mux(T_1469, UInt<3>(7), T_1762) + node T_1764 = mux(T_1467, UInt<3>(7), T_1763) + node T_1765 = mux(T_1465, UInt<3>(7), T_1764) + node T_1766 = mux(T_1463, UInt<3>(7), T_1765) + node T_1767 = mux(T_1461, UInt<3>(7), T_1766) + node T_1768 = mux(T_1459, UInt<3>(7), T_1767) + node T_1769 = mux(T_1457, UInt<3>(7), T_1768) + node T_1770 = mux(T_1455, UInt<3>(4), T_1769) + node T_1771 = mux(T_1453, UInt<3>(0), T_1770) + node T_1772 = mux(T_1451, UInt<3>(5), T_1771) + node T_1773 = mux(T_1449, UInt<3>(1), T_1772) + node T_1774 = mux(T_1447, UInt<3>(6), T_1773) + node T_1775 = mux(T_1445, UInt<3>(2), T_1774) + node T_1776 = mux(T_1443, UInt<3>(7), T_1775) + node T_1777 = mux(T_1441, UInt<3>(7), T_1776) + node T_1778 = mux(T_1439, UInt<3>(7), T_1777) + node T_1779 = mux(T_1437, UInt<3>(7), T_1778) + node T_1780 = mux(T_1521, UInt<1>(0), UInt<1>(0)) + node T_1781 = mux(T_1519, UInt<1>(0), T_1780) + node T_1782 = mux(T_1517, UInt<1>(0), T_1781) + node T_1783 = mux(T_1515, UInt<1>(0), T_1782) + node T_1784 = mux(T_1513, UInt<1>(0), T_1783) + node T_1785 = mux(T_1511, UInt<1>(0), T_1784) + node T_1786 = mux(T_1509, UInt<1>(0), T_1785) + node T_1787 = mux(T_1507, UInt<1>(0), T_1786) + node T_1788 = mux(T_1505, UInt<1>(0), T_1787) + node T_1789 = mux(T_1503, UInt<1>(0), T_1788) + node T_1790 = mux(T_1501, UInt<1>(0), T_1789) + node T_1791 = mux(T_1499, UInt<1>(0), T_1790) + node T_1792 = mux(T_1497, UInt<1>(0), T_1791) + node T_1793 = mux(T_1495, UInt<1>(0), T_1792) + node T_1794 = mux(T_1493, UInt<1>(0), T_1793) + node T_1795 = mux(T_1491, UInt<1>(0), T_1794) + node T_1796 = mux(T_1489, UInt<1>(0), T_1795) + node T_1797 = mux(T_1487, UInt<1>(0), T_1796) + node T_1798 = mux(T_1485, UInt<1>(0), T_1797) + node T_1799 = mux(T_1483, UInt<1>(0), T_1798) + node T_1800 = mux(T_1481, UInt<1>(0), T_1799) + node T_1801 = mux(T_1479, UInt<1>(0), T_1800) + node T_1802 = mux(T_1477, UInt<1>(0), T_1801) + node T_1803 = mux(T_1475, UInt<1>(0), T_1802) + node T_1804 = mux(T_1473, UInt<1>(0), T_1803) + node T_1805 = mux(T_1471, UInt<1>(0), T_1804) + node T_1806 = mux(T_1469, UInt<1>(0), T_1805) + node T_1807 = mux(T_1467, UInt<1>(0), T_1806) + node T_1808 = mux(T_1465, UInt<1>(0), T_1807) + node T_1809 = mux(T_1463, UInt<1>(0), T_1808) + node T_1810 = mux(T_1461, UInt<1>(0), T_1809) + node T_1811 = mux(T_1459, UInt<1>(0), T_1810) + node T_1812 = mux(T_1457, UInt<1>(0), T_1811) + node T_1813 = mux(T_1455, UInt<1>(0), T_1812) + node T_1814 = mux(T_1453, UInt<1>(0), T_1813) + node T_1815 = mux(T_1451, UInt<1>(0), T_1814) + node T_1816 = mux(T_1449, UInt<1>(0), T_1815) + node T_1817 = mux(T_1447, UInt<1>(0), T_1816) + node T_1818 = mux(T_1445, UInt<1>(0), T_1817) + node T_1819 = mux(T_1443, UInt<1>(1), T_1818) + node T_1820 = mux(T_1441, UInt<1>(1), T_1819) + node T_1821 = mux(T_1439, UInt<1>(0), T_1820) + node T_1822 = mux(T_1437, UInt<1>(0), T_1821) + node T_1823 = mux(T_1521, UInt<2>(3), UInt<2>(3)) + node T_1824 = mux(T_1519, UInt<2>(3), T_1823) + node T_1825 = mux(T_1517, UInt<2>(3), T_1824) + node T_1826 = mux(T_1515, UInt<2>(3), T_1825) + node T_1827 = mux(T_1513, UInt<2>(3), T_1826) + node T_1828 = mux(T_1511, UInt<2>(3), T_1827) + node T_1829 = mux(T_1509, UInt<2>(3), T_1828) + node T_1830 = mux(T_1507, UInt<2>(3), T_1829) + node T_1831 = mux(T_1505, UInt<2>(3), T_1830) + node T_1832 = mux(T_1503, UInt<2>(3), T_1831) + node T_1833 = mux(T_1501, UInt<2>(3), T_1832) + node T_1834 = mux(T_1499, UInt<2>(3), T_1833) + node T_1835 = mux(T_1497, UInt<2>(3), T_1834) + node T_1836 = mux(T_1495, UInt<2>(3), T_1835) + node T_1837 = mux(T_1493, UInt<2>(3), T_1836) + node T_1838 = mux(T_1491, UInt<2>(3), T_1837) + node T_1839 = mux(T_1489, UInt<2>(3), T_1838) + node T_1840 = mux(T_1487, UInt<2>(3), T_1839) + node T_1841 = mux(T_1485, UInt<2>(3), T_1840) + node T_1842 = mux(T_1483, UInt<2>(3), T_1841) + node T_1843 = mux(T_1481, UInt<2>(3), T_1842) + node T_1844 = mux(T_1479, UInt<2>(3), T_1843) + node T_1845 = mux(T_1477, UInt<2>(3), T_1844) + node T_1846 = mux(T_1475, UInt<2>(3), T_1845) + node T_1847 = mux(T_1473, UInt<2>(3), T_1846) + node T_1848 = mux(T_1471, UInt<2>(0), T_1847) + node T_1849 = mux(T_1469, UInt<2>(1), T_1848) + node T_1850 = mux(T_1467, UInt<2>(2), T_1849) + node T_1851 = mux(T_1465, UInt<2>(3), T_1850) + node T_1852 = mux(T_1463, UInt<2>(3), T_1851) + node T_1853 = mux(T_1461, UInt<2>(3), T_1852) + node T_1854 = mux(T_1459, UInt<2>(3), T_1853) + node T_1855 = mux(T_1457, UInt<2>(3), T_1854) + node T_1856 = mux(T_1455, UInt<2>(3), T_1855) + node T_1857 = mux(T_1453, UInt<2>(3), T_1856) + node T_1858 = mux(T_1451, UInt<2>(3), T_1857) + node T_1859 = mux(T_1449, UInt<2>(3), T_1858) + node T_1860 = mux(T_1447, UInt<2>(3), T_1859) + node T_1861 = mux(T_1445, UInt<2>(3), T_1860) + node T_1862 = mux(T_1443, UInt<2>(3), T_1861) + node T_1863 = mux(T_1441, UInt<2>(3), T_1862) + node T_1864 = mux(T_1439, UInt<2>(3), T_1863) + node T_1865 = mux(T_1437, UInt<2>(3), T_1864) + node T_1866 = mux(T_1521, UInt<3>(7), UInt<3>(7)) + node T_1867 = mux(T_1519, UInt<3>(7), T_1866) + node T_1868 = mux(T_1517, UInt<3>(7), T_1867) + node T_1869 = mux(T_1515, UInt<3>(7), T_1868) + node T_1870 = mux(T_1513, UInt<3>(7), T_1869) + node T_1871 = mux(T_1511, UInt<3>(7), T_1870) + node T_1872 = mux(T_1509, UInt<3>(7), T_1871) + node T_1873 = mux(T_1507, UInt<3>(7), T_1872) + node T_1874 = mux(T_1505, UInt<3>(7), T_1873) + node T_1875 = mux(T_1503, UInt<3>(7), T_1874) + node T_1876 = mux(T_1501, UInt<3>(7), T_1875) + node T_1877 = mux(T_1499, UInt<3>(7), T_1876) + node T_1878 = mux(T_1497, UInt<3>(7), T_1877) + node T_1879 = mux(T_1495, UInt<3>(7), T_1878) + node T_1880 = mux(T_1493, UInt<3>(7), T_1879) + node T_1881 = mux(T_1491, UInt<3>(7), T_1880) + node T_1882 = mux(T_1489, UInt<3>(7), T_1881) + node T_1883 = mux(T_1487, UInt<3>(7), T_1882) + node T_1884 = mux(T_1485, UInt<3>(7), T_1883) + node T_1885 = mux(T_1483, UInt<3>(7), T_1884) + node T_1886 = mux(T_1481, UInt<3>(7), T_1885) + node T_1887 = mux(T_1479, UInt<3>(7), T_1886) + node T_1888 = mux(T_1477, UInt<3>(7), T_1887) + node T_1889 = mux(T_1475, UInt<3>(7), T_1888) + node T_1890 = mux(T_1473, UInt<3>(7), T_1889) + node T_1891 = mux(T_1471, UInt<3>(7), T_1890) + node T_1892 = mux(T_1469, UInt<3>(7), T_1891) + node T_1893 = mux(T_1467, UInt<3>(7), T_1892) + node T_1894 = mux(T_1465, UInt<3>(3), T_1893) + node T_1895 = mux(T_1463, UInt<3>(4), T_1894) + node T_1896 = mux(T_1461, UInt<3>(0), T_1895) + node T_1897 = mux(T_1459, UInt<3>(1), T_1896) + node T_1898 = mux(T_1457, UInt<3>(2), T_1897) + node T_1899 = mux(T_1455, UInt<3>(7), T_1898) + node T_1900 = mux(T_1453, UInt<3>(7), T_1899) + node T_1901 = mux(T_1451, UInt<3>(7), T_1900) + node T_1902 = mux(T_1449, UInt<3>(7), T_1901) + node T_1903 = mux(T_1447, UInt<3>(7), T_1902) + node T_1904 = mux(T_1445, UInt<3>(7), T_1903) + node T_1905 = mux(T_1443, UInt<3>(7), T_1904) + node T_1906 = mux(T_1441, UInt<3>(7), T_1905) + node T_1907 = mux(T_1439, UInt<3>(7), T_1906) + node T_1908 = mux(T_1437, UInt<3>(7), T_1907) + node T_1909 = mux(T_1521, UInt<2>(3), UInt<2>(0)) + node T_1910 = mux(T_1519, UInt<2>(3), T_1909) + node T_1911 = mux(T_1517, UInt<2>(3), T_1910) + node T_1912 = mux(T_1515, UInt<2>(3), T_1911) + node T_1913 = mux(T_1513, UInt<2>(3), T_1912) + node T_1914 = mux(T_1511, UInt<2>(3), T_1913) + node T_1915 = mux(T_1509, UInt<2>(0), T_1914) + node T_1916 = mux(T_1507, UInt<2>(0), T_1915) + node T_1917 = mux(T_1505, UInt<2>(0), T_1916) + node T_1918 = mux(T_1503, UInt<2>(0), T_1917) + node T_1919 = mux(T_1501, UInt<2>(0), T_1918) + node T_1920 = mux(T_1499, UInt<2>(0), T_1919) + node T_1921 = mux(T_1497, UInt<2>(0), T_1920) + node T_1922 = mux(T_1495, UInt<2>(0), T_1921) + node T_1923 = mux(T_1493, UInt<2>(0), T_1922) + node T_1924 = mux(T_1491, UInt<2>(0), T_1923) + node T_1925 = mux(T_1489, UInt<2>(0), T_1924) + node T_1926 = mux(T_1487, UInt<2>(0), T_1925) + node T_1927 = mux(T_1485, UInt<2>(0), T_1926) + node T_1928 = mux(T_1483, UInt<2>(0), T_1927) + node T_1929 = mux(T_1481, UInt<2>(0), T_1928) + node T_1930 = mux(T_1479, UInt<2>(0), T_1929) + node T_1931 = mux(T_1477, UInt<2>(0), T_1930) + node T_1932 = mux(T_1475, UInt<2>(0), T_1931) + node T_1933 = mux(T_1473, UInt<2>(0), T_1932) + node T_1934 = mux(T_1471, UInt<2>(0), T_1933) + node T_1935 = mux(T_1469, UInt<2>(0), T_1934) + node T_1936 = mux(T_1467, UInt<2>(0), T_1935) + node T_1937 = mux(T_1465, UInt<2>(1), T_1936) + node T_1938 = mux(T_1463, UInt<2>(1), T_1937) + node T_1939 = mux(T_1461, UInt<2>(1), T_1938) + node T_1940 = mux(T_1459, UInt<2>(1), T_1939) + node T_1941 = mux(T_1457, UInt<2>(1), T_1940) + node T_1942 = mux(T_1455, UInt<2>(0), T_1941) + node T_1943 = mux(T_1453, UInt<2>(0), T_1942) + node T_1944 = mux(T_1451, UInt<2>(0), T_1943) + node T_1945 = mux(T_1449, UInt<2>(0), T_1944) + node T_1946 = mux(T_1447, UInt<2>(0), T_1945) + node T_1947 = mux(T_1445, UInt<2>(0), T_1946) + node T_1948 = mux(T_1443, UInt<2>(2), T_1947) + node T_1949 = mux(T_1441, UInt<2>(2), T_1948) + node T_1950 = mux(T_1439, UInt<2>(0), T_1949) + node T_1951 = mux(T_1437, UInt<2>(0), T_1950) + node T_1952 = mux(T_1521, UInt<1>(0), UInt<1>(0)) + node T_1953 = mux(T_1519, UInt<1>(0), T_1952) + node T_1954 = mux(T_1517, UInt<1>(0), T_1953) + node T_1955 = mux(T_1515, UInt<1>(0), T_1954) + node T_1956 = mux(T_1513, UInt<1>(0), T_1955) + node T_1957 = mux(T_1511, UInt<1>(0), T_1956) + node T_1958 = mux(T_1509, UInt<1>(1), T_1957) + node T_1959 = mux(T_1507, UInt<1>(1), T_1958) + node T_1960 = mux(T_1505, UInt<1>(1), T_1959) + node T_1961 = mux(T_1503, UInt<1>(1), T_1960) + node T_1962 = mux(T_1501, UInt<1>(1), T_1961) + node T_1963 = mux(T_1499, UInt<1>(1), T_1962) + node T_1964 = mux(T_1497, UInt<1>(1), T_1963) + node T_1965 = mux(T_1495, UInt<1>(1), T_1964) + node T_1966 = mux(T_1493, UInt<1>(1), T_1965) + node T_1967 = mux(T_1491, UInt<1>(1), T_1966) + node T_1968 = mux(T_1489, UInt<1>(1), T_1967) + node T_1969 = mux(T_1487, UInt<1>(1), T_1968) + node T_1970 = mux(T_1485, UInt<1>(1), T_1969) + node T_1971 = mux(T_1483, UInt<1>(1), T_1970) + node T_1972 = mux(T_1481, UInt<1>(1), T_1971) + node T_1973 = mux(T_1479, UInt<1>(1), T_1972) + node T_1974 = mux(T_1477, UInt<1>(1), T_1973) + node T_1975 = mux(T_1475, UInt<1>(1), T_1974) + node T_1976 = mux(T_1473, UInt<1>(1), T_1975) + node T_1977 = mux(T_1471, UInt<1>(0), T_1976) + node T_1978 = mux(T_1469, UInt<1>(0), T_1977) + node T_1979 = mux(T_1467, UInt<1>(0), T_1978) + node T_1980 = mux(T_1465, UInt<1>(1), T_1979) + node T_1981 = mux(T_1463, UInt<1>(1), T_1980) + node T_1982 = mux(T_1461, UInt<1>(1), T_1981) + node T_1983 = mux(T_1459, UInt<1>(1), T_1982) + node T_1984 = mux(T_1457, UInt<1>(1), T_1983) + node T_1985 = mux(T_1455, UInt<1>(0), T_1984) + node T_1986 = mux(T_1453, UInt<1>(0), T_1985) + node T_1987 = mux(T_1451, UInt<1>(0), T_1986) + node T_1988 = mux(T_1449, UInt<1>(0), T_1987) + node T_1989 = mux(T_1447, UInt<1>(0), T_1988) + node T_1990 = mux(T_1445, UInt<1>(0), T_1989) + node T_1991 = mux(T_1443, UInt<1>(1), T_1990) + node T_1992 = mux(T_1441, UInt<1>(1), T_1991) + node T_1993 = mux(T_1439, UInt<1>(1), T_1992) + node T_1994 = mux(T_1437, UInt<1>(1), T_1993) + node T_1995 = mux(T_1521, UInt<2>(3), UInt<2>(0)) + node T_1996 = mux(T_1519, UInt<2>(2), T_1995) + node T_1997 = mux(T_1517, UInt<2>(1), T_1996) + node T_1998 = mux(T_1515, UInt<2>(3), T_1997) + node T_1999 = mux(T_1513, UInt<2>(2), T_1998) + node T_2000 = mux(T_1511, UInt<2>(1), T_1999) + node T_2001 = mux(T_1509, UInt<2>(0), T_2000) + node T_2002 = mux(T_1507, UInt<2>(0), T_2001) + node T_2003 = mux(T_1505, UInt<2>(0), T_2002) + node T_2004 = mux(T_1503, UInt<2>(0), T_2003) + node T_2005 = mux(T_1501, UInt<2>(0), T_2004) + node T_2006 = mux(T_1499, UInt<2>(0), T_2005) + node T_2007 = mux(T_1497, UInt<2>(0), T_2006) + node T_2008 = mux(T_1495, UInt<2>(0), T_2007) + node T_2009 = mux(T_1493, UInt<2>(0), T_2008) + node T_2010 = mux(T_1491, UInt<2>(0), T_2009) + node T_2011 = mux(T_1489, UInt<2>(0), T_2010) + node T_2012 = mux(T_1487, UInt<2>(0), T_2011) + node T_2013 = mux(T_1485, UInt<2>(0), T_2012) + node T_2014 = mux(T_1483, UInt<2>(0), T_2013) + node T_2015 = mux(T_1481, UInt<2>(0), T_2014) + node T_2016 = mux(T_1479, UInt<2>(0), T_2015) + node T_2017 = mux(T_1477, UInt<2>(0), T_2016) + node T_2018 = mux(T_1475, UInt<2>(0), T_2017) + node T_2019 = mux(T_1473, UInt<2>(0), T_2018) + node T_2020 = mux(T_1471, UInt<2>(0), T_2019) + node T_2021 = mux(T_1469, UInt<2>(0), T_2020) + node T_2022 = mux(T_1467, UInt<2>(0), T_2021) + node T_2023 = mux(T_1465, UInt<2>(0), T_2022) + node T_2024 = mux(T_1463, UInt<2>(0), T_2023) + node T_2025 = mux(T_1461, UInt<2>(0), T_2024) + node T_2026 = mux(T_1459, UInt<2>(0), T_2025) + node T_2027 = mux(T_1457, UInt<2>(0), T_2026) + node T_2028 = mux(T_1455, UInt<2>(0), T_2027) + node T_2029 = mux(T_1453, UInt<2>(0), T_2028) + node T_2030 = mux(T_1451, UInt<2>(0), T_2029) + node T_2031 = mux(T_1449, UInt<2>(0), T_2030) + node T_2032 = mux(T_1447, UInt<2>(0), T_2031) + node T_2033 = mux(T_1445, UInt<2>(0), T_2032) + node T_2034 = mux(T_1443, UInt<2>(0), T_2033) + node T_2035 = mux(T_1441, UInt<2>(0), T_2034) + node T_2036 = mux(T_1439, UInt<2>(0), T_2035) + node T_2037 = mux(T_1437, UInt<2>(0), T_2036) + node rs1_addr = bits(ctrl.inst, 19, 15) + node rs2_addr = bits(ctrl.inst, 24, 20) + reg st_type : UInt<2> + reg ld_type : UInt<3> + reg wb_sel : UInt<2> + node T_2038 = bit(T_1994, 0) + reg wb_en : UInt<1> + reg csr_cmd : UInt<2> + ctrl.pc_sel := T_1564 + node T_2039 = bit-not(ctrl.stall) + node T_2040 = bit-not(ctrl.data_re) + node T_2041 = bit-and(T_2039, T_2040) + ctrl.inst_re := T_2041 + node T_2042 = neq(T_1908, UInt<3>(7)) + node T_2043 = bit(T_1822, 0) + node T_2044 = bit-or(T_2042, T_2043) + node T_2045 = mux(T_2044, UInt<1>(1), UInt<1>(0)) + ctrl.inst_type := T_2045 + ctrl.A_sel := T_1607 + ctrl.B_sel := T_1650 + ctrl.imm_sel := T_1693 + ctrl.alu_op := T_1736 + ctrl.br_type := T_1779 + ctrl.st_type := T_1865 + node T_2046 = bit-not(ctrl.stall) + when T_2046 : + st_type := ctrl.st_type + ld_type := T_1908 + wb_sel := T_1951 + node T_2047 = bit(T_1994, 0) + wb_en := T_2047 + csr_cmd := T_2037 + node T_2048 = neq(ctrl.ld_type, UInt<3>(7)) + node T_2049 = neq(T_1908, UInt<3>(7)) + node T_2050 = mux(ctrl.stall, T_2048, T_2049) + ctrl.data_re := T_2050 + ctrl.ld_type := ld_type + ctrl.wb_en := wb_en + ctrl.wb_sel := wb_sel + ctrl.csr_cmd := csr_cmd + module Core : + output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>} + output icache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} + output dcache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} + input stall : UInt<1> + + inst dpath of Datapath + inst ctrl of Control + host := dpath.host + icache := dpath.icache + dcache := dpath.dcache + dpath.ctrl := ctrl.ctrl + dpath.stall := stall |