1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
|
; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
;CHECK: Done!
circuit Datapath :
module ALU :
input B : UInt<32>
output out : UInt<32>
output sum : UInt<32>
input A : UInt<32>
input alu_op : UInt<4>
node shamt = bits(B, 4, 0)
node T_433 = add-wrap(A, B)
node T_434 = sub-wrap(A, B)
node T_435 = convert(A)
node T_436 = dshr(T_435, shamt)
node T_437 = as-UInt(T_436)
node T_438 = dshr(A, shamt)
node T_439 = dshl(A, shamt)
node T_440 = bits(T_439, 31, 0)
node T_441 = convert(A)
node T_442 = convert(B)
node T_443 = lt(T_441, T_442)
node T_444 = as-UInt(T_443)
node T_445 = lt(A, B)
node T_446 = as-UInt(T_445)
node T_447 = bit-and(A, B)
node T_448 = bit-or(A, B)
node T_449 = bit-xor(A, B)
node T_450 = eq(UInt<4>(10), alu_op)
node T_451 = mux(T_450, A, B)
node T_452 = eq(UInt<4>(4), alu_op)
node T_453 = mux(T_452, T_449, T_451)
node T_454 = eq(UInt<4>(3), alu_op)
node T_455 = mux(T_454, T_448, T_453)
node T_456 = eq(UInt<4>(2), alu_op)
node T_457 = mux(T_456, T_447, T_455)
node T_458 = eq(UInt<4>(7), alu_op)
node T_459 = mux(T_458, T_446, T_457)
node T_460 = eq(UInt<4>(5), alu_op)
node T_461 = mux(T_460, T_444, T_459)
node T_462 = eq(UInt<4>(6), alu_op)
node T_463 = mux(T_462, T_440, T_461)
node T_464 = eq(UInt<4>(8), alu_op)
node T_465 = mux(T_464, T_438, T_463)
node T_466 = eq(UInt<4>(9), alu_op)
node T_467 = mux(T_466, T_437, T_465)
node T_468 = eq(UInt<4>(1), alu_op)
node T_469 = mux(T_468, T_434, T_467)
node T_470 = eq(UInt<4>(0), alu_op)
node oot = mux(T_470, T_433, T_469)
node T_471 = bits(oot, 31, 0)
out := T_471
node T_472 = bit(alu_op, 0)
node T_473 = sub-wrap(UInt<1>(0), B)
node T_474 = mux(T_472, T_473, B)
node T_475 = add-wrap(A, T_474)
sum := T_475
module BrCond :
input rs1 : UInt<32>
input rs2 : UInt<32>
output taken : UInt<1>
input br_type : UInt<3>
node eq = eq(rs1, rs2)
node neq = bit-not(eq)
node T_476 = convert(rs1)
node T_477 = convert(rs2)
node lt = lt(T_476, T_477)
node ge = bit-not(lt)
node ltu = lt(rs1, rs2)
node geu = bit-not(ltu)
node T_478 = eq(br_type, UInt<3>(2))
node T_479 = bit-and(T_478, eq)
node T_480 = eq(br_type, UInt<3>(6))
node T_481 = bit-and(T_480, neq)
node T_482 = bit-or(T_479, T_481)
node T_483 = eq(br_type, UInt<3>(1))
node T_484 = bit-and(T_483, lt)
node T_485 = bit-or(T_482, T_484)
node T_486 = eq(br_type, UInt<3>(5))
node T_487 = bit-and(T_486, ge)
node T_488 = bit-or(T_485, T_487)
node T_489 = eq(br_type, UInt<3>(0))
node T_490 = bit-and(T_489, ltu)
node T_491 = bit-or(T_488, T_490)
node T_492 = eq(br_type, UInt<3>(4))
node T_493 = bit-and(T_492, geu)
node T_494 = bit-or(T_491, T_493)
taken := T_494
module RegFile :
input raddr1 : UInt<5>
input raddr2 : UInt<5>
output rdata1 : UInt<32>
output rdata2 : UInt<32>
input wen : UInt<1>
input waddr : UInt<5>
input wdata : UInt<32>
cmem regs : UInt<32>[32]
node T_495 = eq(raddr1, UInt<1>(0))
node T_496 = bit-not(T_495)
accessor T_497 = regs[raddr1]
node T_498 = mux(T_496, T_497, UInt<1>(0))
rdata1 := T_498
node T_499 = eq(raddr2, UInt<1>(0))
node T_500 = bit-not(T_499)
accessor T_501 = regs[raddr2]
node T_502 = mux(T_500, T_501, UInt<1>(0))
rdata2 := T_502
node T_503 = eq(waddr, UInt<1>(0))
node T_504 = bit-not(T_503)
node T_505 = bit-and(wen, T_504)
when T_505 :
accessor T_506 = regs[waddr]
T_506 := wdata
module ImmGenWire :
output out : UInt<32>
input inst : UInt<32>
input sel : UInt<3>
node T_507 = bits(inst, 31, 20)
node Iimm = convert(T_507)
node T_508 = bits(inst, 31, 25)
node T_509 = bits(inst, 11, 7)
node T_510 = cat(T_508, T_509)
node Simm = convert(T_510)
node T_511 = bit(inst, 31)
node T_512 = bit(inst, 7)
node T_513 = bits(inst, 30, 25)
node T_514 = bits(inst, 11, 8)
node T_515 = cat(T_511, T_512)
node T_516 = cat(T_514, UInt<1>(0))
node T_517 = cat(T_513, T_516)
node T_518 = cat(T_515, T_517)
node Bimm = convert(T_518)
node T_519 = bits(inst, 31, 12)
node T_520 = cat(T_519, UInt<12>(0))
node Uimm = convert(T_520)
node T_521 = bit(inst, 31)
node T_522 = bits(inst, 19, 12)
node T_523 = bit(inst, 20)
node T_524 = bits(inst, 30, 25)
node T_525 = bits(inst, 24, 21)
node T_526 = cat(T_522, T_523)
node T_527 = cat(T_521, T_526)
node T_528 = cat(T_525, UInt<1>(0))
node T_529 = cat(T_524, T_528)
node T_530 = cat(T_527, T_529)
node Jimm = convert(T_530)
node T_531 = bits(inst, 19, 15)
node T_532 = pad(T_531, 32)
node Zimm = convert(T_532)
node T_533 = eq(UInt<3>(3), sel)
node T_534 = mux(T_533, Jimm, Zimm)
node T_535 = eq(UInt<3>(2), sel)
node T_536 = mux(T_535, Uimm, T_534)
node T_537 = eq(UInt<3>(4), sel)
node T_538 = mux(T_537, Bimm, T_536)
node T_539 = eq(UInt<3>(1), sel)
node T_540 = mux(T_539, Simm, T_538)
node T_541 = eq(UInt<3>(0), sel)
node T_542 = mux(T_541, Iimm, T_540)
node T_543 = as-UInt(T_542)
out := T_543
module CSR :
output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>}
input src : UInt<32>
input cmd : UInt<2>
output data : UInt<32>
input addr : UInt<12>
reg reg_tohost : UInt<32>
on-reset reg_tohost := UInt<32>(0)
reg reg_status : UInt<32>
on-reset reg_status := UInt<32>(0)
host.tohost := reg_tohost
host.status := reg_status
node T_544 = eq(UInt<12>(1291), addr)
node T_545 = mux(T_544, host.hid, UInt<1>(0))
node T_546 = eq(UInt<12>(1290), addr)
node T_547 = mux(T_546, reg_status, T_545)
node T_548 = eq(UInt<12>(1310), addr)
node T_549 = mux(T_548, reg_tohost, T_547)
data := T_549
node T_550 = eq(cmd, UInt<2>(1))
when T_550 :
node T_551 = eq(addr, UInt<12>(1310))
when T_551 : reg_tohost := src
node T_552 = eq(addr, UInt<12>(1290))
when T_552 : reg_status := src
node T_553 = eq(cmd, UInt<2>(2))
node T_554 = neq(src, UInt<1>(0))
node T_555 = bit-and(T_553, T_554)
when T_555 :
node T_556 = eq(addr, UInt<12>(1310))
when T_556 :
node T_557 = dshl(UInt<1>(1), src)
node T_558 = bit-or(data, T_557)
reg_tohost := T_558
node T_559 = eq(addr, UInt<12>(1290))
when T_559 :
node T_560 = dshl(UInt<1>(1), src)
node T_561 = bit-or(data, T_560)
reg_status := T_561
node T_562 = eq(cmd, UInt<2>(3))
node T_563 = neq(src, UInt<1>(0))
node T_564 = bit-and(T_562, T_563)
when T_564 :
node T_565 = eq(addr, UInt<12>(1310))
when T_565 :
node T_566 = dshl(UInt<1>(0), src)
node T_567 = bit-and(data, T_566)
reg_tohost := T_567
node T_568 = eq(addr, UInt<12>(1290))
when T_568 :
node T_569 = dshl(UInt<1>(0), src)
node T_570 = bit-and(data, T_569)
reg_status := T_570
module Datapath :
output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>}
input ctrl : {flip inst : UInt<32>, pc_sel : UInt<1>, inst_type : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, imm_sel : UInt<3>, wb_en : UInt<1>, wb_sel : UInt<2>, A_sel : UInt<1>, B_sel : UInt<1>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, csr_cmd : UInt<2>}
output icache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
output dcache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
input stall : UInt<1>
inst alu of ALU
inst brCond of BrCond
inst regFile of RegFile
inst immGen of ImmGenWire
reg fe_inst : UInt<32>
on-reset fe_inst := UInt<32>(0)
reg fe_pc : UInt
reg ew_inst : UInt<32>
on-reset ew_inst := UInt<32>(0)
reg ew_pc : UInt
reg ew_alu : UInt
node T_571 = sub-wrap(UInt<14>(8192), UInt<32>(4))
reg pc : UInt<32>
on-reset pc := T_571
node T_572 = eq(ctrl.pc_sel, UInt<1>(1))
node T_573 = bit-or(T_572, brCond.taken)
node T_574 = add-wrap(pc, UInt<3>(4))
node iaddr = mux(T_573, alu.sum, T_574)
node T_575 = eq(ctrl.inst_type, UInt<1>(1))
node T_576 = bit-or(T_575, brCond.taken)
node inst = mux(T_576, UInt<32>(19), icache.dout)
icache.we := UInt<1>(0)
icache.din := UInt<1>(0)
icache.addr := iaddr
icache.re := ctrl.inst_re
node T_577 = eq(dcache.we, UInt<1>(0))
node T_578 = bit-not(T_577)
node T_579 = bit-not(T_578)
node T_580 = bit-and(icache.re, T_579)
node T_581 = mux(T_580, iaddr, pc)
pc := T_581
node T_582 = bit-not(stall)
when T_582 :
fe_pc := pc
fe_inst := inst
ctrl.inst := fe_inst
ctrl.stall := stall
node rd_addr = bits(fe_inst, 11, 7)
node rs1_addr = bits(fe_inst, 19, 15)
node rs2_addr = bits(fe_inst, 24, 20)
regFile.raddr1 := rs1_addr
regFile.raddr2 := rs2_addr
immGen.inst := fe_inst
immGen.sel := ctrl.imm_sel
node T_583 = eq(rs1_addr, UInt<1>(0))
node rs1NotZero = bit-not(T_583)
node T_584 = eq(rs2_addr, UInt<1>(0))
node rs2NotZero = bit-not(T_584)
node T_585 = eq(ctrl.wb_sel, UInt<2>(0))
node alutype = bit-and(ctrl.wb_en, T_585)
node ex_rd_addr = bits(ew_inst, 11, 7)
node T_586 = bit-and(alutype, rs1NotZero)
node T_587 = eq(rs1_addr, ex_rd_addr)
node T_588 = bit-and(T_586, T_587)
node rs1 = mux(T_588, ew_alu, regFile.rdata1)
node T_589 = bit-and(alutype, rs2NotZero)
node T_590 = eq(rs2_addr, ex_rd_addr)
node T_591 = bit-and(T_589, T_590)
node rs2 = mux(T_591, ew_alu, regFile.rdata2)
node T_592 = eq(ctrl.A_sel, UInt<1>(0))
node T_593 = mux(T_592, rs1, fe_pc)
alu.A := T_593
node T_594 = eq(ctrl.B_sel, UInt<1>(0))
node T_595 = mux(T_594, rs2, immGen.out)
alu.B := T_595
alu.alu_op := ctrl.alu_op
brCond.rs1 := rs1
brCond.rs2 := rs2
brCond.br_type := ctrl.br_type
node T_596 = bit(alu.sum, 1)
node T_597 = dshl(T_596, UInt<3>(4))
node T_598 = bit(alu.sum, 0)
node T_599 = dshl(T_598, UInt<2>(3))
node woffset = bit-or(T_597, T_599)
dcache.re := ctrl.data_re
node T_600 = mux(stall, ew_alu, alu.sum)
dcache.addr := T_600
node T_601 = bits(alu.sum, 1, 0)
node T_602 = dshl(UInt<2>(3), T_601)
node T_603 = bits(T_602, 3, 0)
node T_604 = bits(alu.sum, 1, 0)
node T_605 = dshl(UInt<1>(1), T_604)
node T_606 = bits(T_605, 3, 0)
node T_607 = eq(UInt<2>(2), ctrl.st_type)
node T_608 = mux(T_607, T_606, UInt<4>(0))
node T_609 = eq(UInt<2>(1), ctrl.st_type)
node T_610 = mux(T_609, T_603, T_608)
node T_611 = eq(UInt<2>(0), ctrl.st_type)
node T_612 = mux(T_611, UInt<4>(15), T_610)
node T_613 = mux(stall, UInt<4>(0), T_612)
dcache.we := T_613
node T_614 = dshl(rs2, woffset)
node T_615 = bits(T_614, 31, 0)
dcache.din := T_615
node T_616 = bit-not(stall)
when T_616 :
ew_pc := fe_pc
ew_inst := fe_inst
ew_alu := alu.out
node T_617 = bit(ew_alu, 1)
node T_618 = dshl(T_617, UInt<3>(4))
node T_619 = bit(ew_alu, 0)
node T_620 = dshl(T_619, UInt<2>(3))
node loffset = bit-or(T_618, T_620)
node lshift = dshr(dcache.dout, loffset)
node T_621 = bits(lshift, 15, 0)
node T_622 = convert(T_621)
node T_623 = pad(T_622, 32)
node T_624 = as-UInt(T_623)
node T_625 = bits(lshift, 7, 0)
node T_626 = convert(T_625)
node T_627 = pad(T_626, 32)
node T_628 = as-UInt(T_627)
node T_629 = bits(lshift, 15, 0)
node T_630 = bits(lshift, 7, 0)
node T_631 = eq(UInt<3>(4), ctrl.ld_type)
node T_632 = mux(T_631, T_630, dcache.dout)
node T_633 = eq(UInt<3>(3), ctrl.ld_type)
node T_634 = mux(T_633, T_629, T_632)
node T_635 = eq(UInt<3>(2), ctrl.ld_type)
node T_636 = mux(T_635, T_628, T_634)
node T_637 = eq(UInt<3>(1), ctrl.ld_type)
node load = mux(T_637, T_624, T_636)
inst csr of CSR
host := csr.host
csr.src := ew_alu
node T_638 = bits(ew_inst, 31, 20)
csr.addr := T_638
csr.cmd := ctrl.csr_cmd
node T_639 = add-wrap(ew_pc, UInt<3>(4))
node T_640 = eq(UInt<2>(3), ctrl.wb_sel)
node T_641 = mux(T_640, csr.data, ew_alu)
node T_642 = eq(UInt<2>(2), ctrl.wb_sel)
node T_643 = mux(T_642, T_639, T_641)
node T_644 = eq(UInt<2>(1), ctrl.wb_sel)
node regWrite = mux(T_644, load, T_643)
regFile.wen := ctrl.wb_en
regFile.waddr := ex_rd_addr
regFile.wdata := regWrite
|
