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Diffstat (limited to 'test/chisel3/ModuleWire.fir')
| -rw-r--r-- | test/chisel3/ModuleWire.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir index fefe42bd..3be7f928 100644 --- a/test/chisel3/ModuleWire.fir +++ b/test/chisel3/ModuleWire.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s ;CHECK: Done! circuit ModuleWire : |