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2016-09-07Add Printable (#270)Jack Koenig
Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types
2016-09-06Verify we can suppress the inclusion of default compileOptions.Jim Lawson
2016-09-02Rename implicit compileOptions to defaultCompileOptions.Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
Eliminate builder compileOptions.
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Make compileOptions in the Chisel package effective.Jim Lawson
Remove references to the Chisel package in favor of explicit chisel3 imports in tests,
2016-08-30Explicitly clone the target type in noenq() to avoid "already bound" errors ↵Jim Lawson
for io ports.
2016-08-30Add example of specific CompileOptions settings to tests.Jim Lawson
2016-08-30Add abstract classes with explicit connection checking options.Jim Lawson
2016-08-30Allow compileOptions as optional arguments to elaborate() and emit().Jim Lawson
2016-08-30Correct parameter name (topModule) in ScalaDoc.Jim Lawson
2016-08-29Check module-specific compile options.Jim Lawson
Import chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests.
2016-08-29Rename CompileOptions implicit objects.Jim Lawson
2016-08-29Pass compileOptions as an implicit Module parameter.Jim Lawson
2016-08-25fix a bug in setModNameDonggyu Kim
2016-08-24Per Chisel meeting.chick
signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR
2016-08-22Purely cosmetic changes to placate the scalastyle checker.Jim Lawson
2016-08-22Fix firrtlDirection for class DeqIO.Jim Lawson
2016-08-21AnnotatingExample:chick
Removed extraneous logic Renamed doStuff to buildAnnotatedCircuit Removed println's
2016-08-21Add AnnotationSpec file which provides an example of a way to implement ↵chick
generation of annotations in a chisel circuit that could be used by custom firrtl passes This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module
2016-08-21Add annotating example to test new signal name apichick
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
* signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name.
2016-08-18Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_testsJim Lawson
Revive support for firrtl flip direction. Remove compileOptions.internalConnectionToInputOk
2016-08-17Reduce rocket-chip elaboration errors.Jim Lawson
2016-08-16Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
* Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths
2016-08-11Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one.
2016-08-09counter(inc,n) example should reflect actual use (#252)Colin Schmidt
2016-08-03Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-03Merge "package" code into "compatibility".Jim Lawson
2016-07-31Remove deprecated FileSystemUtilitiesAndrew Waterman
This has been deprecated for a long time now (and really shouldn't have existed to begin with).
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-28Add missing Decoupled object pointer.Jim Lawson
2016-07-27More compatibility fixesJim Lawson
2016-07-27Correct EnqIO/DeqIO Flipped-ness.Jim Lawson
2016-07-27Correct EnqIO/DeqIO Flipped-ness.Jim Lawson
2016-07-27Additional compatibility code.Jim Lawson
2016-07-27Correct EnqIO/DeqIO Flipped-ness.Jim Lawson
2016-07-27Correct EnqIO/DeqIO Flipped-ness.Jim Lawson
2016-07-26Add ValidIO definition for old code.Jim Lawson
2016-07-25Enable current (chisel2-style) compatibility mode.Jim Lawson
2016-07-25Minimize differences with master.Jim Lawson
Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition.
2016-07-25Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-25Use more idiomatic ScalaTest exception expecting code.Jim Lawson
2016-07-25Add missing compatibility.scala.Jim Lawson
2016-07-25catch Bad connection exceptionJim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
Still fails one test - DirectionSpec in Direction.scala
2016-07-21Ensure test_wire is sinkable.Jim Lawson
2016-07-20More literal/width rangling.Jim Lawson
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