Minimize differences with master.

Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.

29 files changed, 124 insertions, 122 deletions

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index b7020b5e..041553e0 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -7,6 +7,7 @@ package object Chisel {
   type Direction = chisel3.core.Direction
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
+  val NODIR = chisel3.core.Direction.Unspecified
   object Flipped {
     def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target)
   }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 9a79b109..774455c4 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -95,7 +95,7 @@ package object chisel3 {
     def asSInt(width: Int) = SInt(x, width)
   }
   implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt.Lit(x)
+    def U: UInt = UInt(x)
   }
   implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
     def B: Bool = Bool(x)
@@ -113,5 +113,6 @@ package object chisel3 {
 
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
+  val NODIR = chisel3.core.Direction.Unspecified
   type ChiselException = chisel3.internal.ChiselException
 }
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 0ece3a0a..5875b3f2 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -36,17 +36,17 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
   if (count > 1) {
     val lockCount = Counter(count)
     val lockIdx = Reg(UInt())
-    val locked = lockCount.value =/= UInt.Lit(0)
+    val locked = lockCount.value =/= UInt(0)
     val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
 
-    when (io.out.firing && wantsLock) {
+    when (io.out.fire() && wantsLock) {
       lockIdx := io.chosen
       lockCount.inc()
     }
 
     when (locked) { io.chosen := lockIdx }
     for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
-      in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready
+      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
   } else {
     for ((in, g) <- io.in zip grant)
       in.ready := g && io.out.ready
@@ -55,8 +55,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
-  lazy val lastGrant = RegEnable(io.chosen, io.out.firing)
-  lazy val grantMask = (0 until n).map(UInt.Lit(_) > lastGrant)
+  lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
+  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
   lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
 
   override def grant: Seq[Bool] = {
@@ -64,20 +64,20 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
     (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
   }
 
-  override lazy val choice = Wire(init=UInt.Lit(n-1))
+  override lazy val choice = Wire(init=UInt(n-1))
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt.Lit(i) }
+    when (io.in(i).valid) { choice := UInt(i) }
   for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := UInt.Lit(i) }
+    when (validMask(i)) { choice := UInt(i) }
 }
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
 
-  override lazy val choice = Wire(init=UInt.Lit(n-1))
+  override lazy val choice = Wire(init=UInt(n-1))
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt.Lit(i) }
+    when (io.in(i).valid) { choice := UInt(i) }
 }
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -103,11 +103,11 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
 class Arbiter[T <: Data](gen: T, n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
-  io.chosen := UInt.Lit(n-1)
+  io.chosen := UInt(n-1)
   io.out.bits := io.in(n-1).bits
   for (i <- n-2 to 0 by -1) {
     when (io.in(i).valid) {
-      io.chosen := UInt.Lit(i)
+      io.chosen := UInt(i)
       io.out.bits := io.in(i).bits
     }
   }
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 27bd7bfb..c809e14b 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -16,11 +16,11 @@ object Log2 {
   /** Compute the Log2 on the least significant n bits of x */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
-      UInt.Lit(0)
+      UInt(0)
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt.Lit(width-1), apply(x, width-1))
+      Mux(x(width-1), UInt(width-1), apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 05d8fba8..40615769 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -10,17 +10,17 @@ import chisel3._
   */
 class Counter(val n: Int) {
   require(n >= 0)
-  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt.Lit(0)
+  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
   /** Increment the counter, returning whether the counter currently is at the
     * maximum and will wrap. The incremented value is registered and will be
     * visible on the next cycle.
     */
   def inc(): Bool = {
     if (n > 1) {
-      val wrap = value === UInt.Lit(n-1)
-      value := value + UInt.Lit(1)
+      val wrap = value === UInt(n-1)
+      value := value + UInt(1)
       if (!isPow2(n)) {
-        when (wrap) { value := UInt.Lit(0) }
+        when (wrap) { value := UInt(0) }
       }
       wrap
     } else {
@@ -33,7 +33,7 @@ class Counter(val n: Int) {
   * Example Usage:
   * {{{ val countOn = Bool(true) // increment counter every clock cycle
   * val myCounter = Counter(countOn, n)
-  * when ( myCounter.value === UInt.Lit(3) ) { ... } }}}*/
+  * when ( myCounter.value === UInt(3) ) { ... } }}}*/
 object Counter
 {
   def apply(n: Int): Counter = new Counter(n)
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 76bf4842..68c3ae88 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -23,7 +23,7 @@ object DecoupledIO {
   def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
 
   implicit class AddMethodsToDecoupled[T<:Data](val target: DecoupledIO[T]) extends AnyVal {
-    def firing: Bool = target.ready && target.valid
+    def fire(): Bool = target.ready && target.valid
 
     /** push dat onto the output bits of this interface to let the consumer know it has happened.
       * @param dat the values to assign to bits.
@@ -114,8 +114,8 @@ extends Module(override_reset=override_reset) {
   val ptr_match = enq_ptr.value === deq_ptr.value
   val empty = ptr_match && !maybe_full
   val full = ptr_match && maybe_full
-  val do_enq = Wire(init=io.enq.firing)
-  val do_deq = Wire(init=io.deq.firing)
+  val do_enq = Wire(init=io.enq.fire())
+  val do_deq = Wire(init=io.deq.fire())
 
   when (do_enq) {
     ram(enq_ptr.value) := io.enq.bits
@@ -151,9 +151,9 @@ extends Module(override_reset=override_reset) {
   } else {
     io.count := Mux(ptr_match,
                     Mux(maybe_full,
-                      UInt.Lit(entries), UInt.Lit(0)),
+                      UInt(entries), UInt(0)),
                     Mux(deq_ptr.value > enq_ptr.value,
-                      UInt.Lit(entries) + ptr_diff, ptr_diff))
+                      UInt(entries) + ptr_diff, ptr_diff))
   }
 }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 3a9089c5..4d816a19 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,6 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
-  implicit def intToUInt(x: Int): UInt = UInt.Lit(x)
+  implicit def intToUInt(x: Int): UInt = UInt(x)
   implicit def booleanToBool(x: Boolean): Bool = Bool(x)
 }
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 49661115..abede61e 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -31,7 +31,7 @@ object OHToUInt {
   * @example {{{ data_out := PriorityEncoder(data_in) }}}
   */
 object PriorityEncoder {
-  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt.Lit(_)))
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
   def apply(in: Bits): UInt = apply(in.toBools)
 }
 
@@ -41,9 +41,9 @@ object UIntToOH
 {
   def apply(in: UInt, width: Int = -1): UInt =
     if (width == -1) {
-      UInt.Lit(1) << in
+      UInt(1) << in
     } else {
-      (UInt.Lit(1) << in(log2Up(width)-1,0))(width-1,0)
+      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
     }
 }
 
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index bf3c8092..efc2e1e7 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester {
 
 class PipelinedResetModule extends Module {
   val io = IO(new Bundle { })
-  val a = Reg(init = UInt.Lit(0xbeef))
-  val b = Reg(init = UInt.Lit(0xbeef))
+  val a = Reg(init = UInt(0xbeef))
+  val b = Reg(init = UInt(0xbeef))
   assert(a === b)
 }
 
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 0aaa3c57..08999a1b 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -11,10 +11,10 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
   val a = UInt(_a, w)
   val b = UInt(_b, w)
-  assert(~a === UInt.Lit(mask & ~_a))
-  assert((a & b) === UInt.Lit(_a & _b))
-  assert((a | b) === UInt.Lit(_a | _b))
-  assert((a ^ b) === UInt.Lit(_a ^ _b))
+  assert(~a === UInt(mask & ~_a))
+  assert((a & b) === UInt(_a & _b))
+  assert((a | b) === UInt(_a | _b))
+  assert((a ^ b) === UInt(_a ^ _b))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 9b43f0ef..c1154883 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -35,11 +35,11 @@ class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
 
-  blackBoxPos.io.in := UInt.Lit(1)
-  blackBoxNeg.io.in := UInt.Lit(0)
+  blackBoxPos.io.in := UInt(1)
+  blackBoxNeg.io.in := UInt(0)
 
-  assert(blackBoxNeg.io.out === UInt.Lit(1))
-  assert(blackBoxPos.io.out === UInt.Lit(0))
+  assert(blackBoxNeg.io.out === UInt(1))
+  assert(blackBoxPos.io.out === UInt(0))
   stop()
 }
 
@@ -54,15 +54,15 @@ class MultiBlackBoxTester extends BasicTester {
   val blackBoxPassPos = Module(new BlackBoxPassthrough)
   val blackBoxPassNeg = Module(new BlackBoxPassthrough)
 
-  blackBoxInvPos.io.in := UInt.Lit(1)
-  blackBoxInvNeg.io.in := UInt.Lit(0)
-  blackBoxPassPos.io.in := UInt.Lit(1)
-  blackBoxPassNeg.io.in := UInt.Lit(0)
+  blackBoxInvPos.io.in := UInt(1)
+  blackBoxInvNeg.io.in := UInt(0)
+  blackBoxPassPos.io.in := UInt(1)
+  blackBoxPassNeg.io.in := UInt(0)
 
-  assert(blackBoxInvNeg.io.out === UInt.Lit(1))
-  assert(blackBoxInvPos.io.out === UInt.Lit(0))
-  assert(blackBoxPassNeg.io.out === UInt.Lit(0))
-  assert(blackBoxPassPos.io.out === UInt.Lit(1))
+  assert(blackBoxInvNeg.io.out === UInt(1))
+  assert(blackBoxInvPos.io.out === UInt(0))
+  assert(blackBoxPassNeg.io.out === UInt(0))
+  assert(blackBoxPassPos.io.out === UInt(1))
   stop()
 }
 
@@ -77,7 +77,7 @@ class BlackBoxWithClockTester extends BasicTester {
   blackBox.io.in := impetus
   model := impetus
 
-  when(cycles > UInt.Lit(0)) {
+  when(cycles > UInt(0)) {
     assert(blackBox.io.out === model)
   }
   when(end) { stop() }
@@ -98,8 +98,8 @@ class BlackBoxWithParamsTester extends BasicTester {
 
   val (cycles, end) = Counter(Bool(true), 4)
 
-  assert(blackBoxOne.io.out  === UInt.Lit(1))
-  assert(blackBoxFour.io.out === UInt.Lit(4))
+  assert(blackBoxOne.io.out  === UInt(1))
+  assert(blackBoxFour.io.out === UInt(4))
 
   when(end) { stop() }
 }
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 3d3d58f3..0071041c 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -25,11 +25,11 @@ class BundleWire(n: Int) extends Module {
 
 class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new BundleWire(n))
-  dut.io.in.x := UInt.Lit(x)
-  dut.io.in.y := UInt.Lit(y)
+  dut.io.in.x := UInt(x)
+  dut.io.in.y := UInt(y)
   for (elt <- dut.io.outs) {
-    assert(elt.x === UInt.Lit(x))
-    assert(elt.y === UInt.Lit(y))
+    assert(elt.x === UInt(x))
+    assert(elt.y === UInt(y))
   }
   stop()
 }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index fce2c602..0a1f31cc 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -26,19 +26,19 @@ class ComplexAssign(w: Int) extends Module {
     io.out.re := tmp.re
     io.out.im := tmp.im
   } .otherwise {
-    io.out.re := UInt.Lit(0)
-    io.out.im := UInt.Lit(0)
+    io.out.re := UInt(0)
+    io.out.im := UInt(0)
   }
 }
 
 class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), enList.size)
   val dut = Module(new ComplexAssign(32))
-  dut.io.in.re := UInt.Lit(re)
-  dut.io.in.im := UInt.Lit(im)
+  dut.io.in.re := UInt(re)
+  dut.io.in.im := UInt(im)
   dut.io.e := Vec(enList.map(Bool(_)))(cnt)
-  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt.Lit(0))
-  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt.Lit(0))
+  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0))
+  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0))
   assert(re_correct && im_correct)
   when(wrap) {
     stop()
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index af2fa550..69d8a44a 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -12,20 +12,20 @@ import chisel3.util._
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
   when(Bool(true)) { cnt.inc() }
-  when(cnt.value === UInt.Lit(max-1)) {
+  when(cnt.value === UInt(max-1)) {
     stop()
   }
 }
 
 class EnableTester(seed: Int) extends BasicTester {
-  val ens = Reg(init = UInt.Lit(seed))
+  val ens = Reg(init = UInt(seed))
   ens := ens >> 1
 
   val (cntEnVal, _) = Counter(ens(0), 32)
   val (_, done) = Counter(Bool(true), 33)
 
   when(done) {
-    assert(cntEnVal === UInt.Lit(popCount(seed)))
+    assert(cntEnVal === UInt(popCount(seed)))
     stop()
   }
 }
@@ -33,7 +33,7 @@ class EnableTester(seed: Int) extends BasicTester {
 class WrapTester(max: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), max)
   when(wrap) {
-    assert(cnt === UInt.Lit(max - 1))
+    assert(cnt === UInt(max - 1))
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index ee892fc5..b50a80c0 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -24,7 +24,7 @@ class DecoderTester(pairs: List[(String, String)]) extends BasicTester {
   val dut = Module(new Decoder(bitpats))
   dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
   when(!dut.io.matched) {
-    assert(cnt === UInt.Lit(0))
+    assert(cnt === UInt(0))
     stop()
   }
   when(wrap) {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 2fe31475..83484a64 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -15,11 +15,11 @@ class DirectionHaver extends Module {
 }
 
 class GoodDirection extends DirectionHaver {
-  io.out := UInt.Lit(0)
+  io.out := UInt(0)
 }
 
 class BadDirection extends DirectionHaver {
-  io.in := UInt.Lit(0)
+  io.in := UInt(0)
 }
 
 class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index e4063532..1d09f3c5 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -17,11 +17,11 @@ class MemorySearch extends Module {
   val elts  = Vec(vals.map(UInt(_,4)))
   // val elts  = Mem(UInt(width = 32), 8) TODO ????
   val elt  = elts(index)
-  val end  = !io.en && ((elt === io.target) || (index === UInt.Lit(7)))
+  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
   when (io.en) {
-    index := UInt.Lit(0)
+    index := UInt(0)
   } .elsewhen (!end) {
-    index := index +% UInt.Lit(1)
+    index := index +% UInt(1)
   }
   io.done    := end
   io.address := index
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 26953f5f..7a4050db 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -16,8 +16,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Input(Vec(n, UInt.Lit(32)))
-    val outs = Output(Vec(n, UInt.Lit(32)))
+    val ins  = Input(Vec(n, UInt(32)))
+    val outs = Output(Vec(n, UInt(32)))
   })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 16a29104..26ee4e03 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -24,9 +24,9 @@ class MulLookup(val w: Int) extends Module {
 
 class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
-  dut.io.x := UInt.Lit(x)
-  dut.io.y := UInt.Lit(y)
-  assert(dut.io.z === UInt.Lit(x * y))
+  dut.io.x := UInt(x)
+  dut.io.y := UInt(y)
+  assert(dut.io.z === UInt(x * y))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index 92b6fee1..c872fde4 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
-  val x = UInt.Lit(254)
+  val x = UInt(254)
   printf("x=%x", x)
   stop()
 }
@@ -18,8 +18,8 @@ class ASCIIPrintfTester() extends BasicTester {
 }
 
 class MultiPrintfTester() extends BasicTester {
-  val x = UInt.Lit(254)
-  val y = UInt.Lit(255)
+  val x = UInt(254)
+  val y = UInt(255)
   printf("x=%x y=%x", x, y)
   stop()
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 8b9016b1..b66d7cb4 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20))
+      val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt(20))
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 665bb8e6..6d5a0a76 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -38,7 +38,7 @@ class Risc extends Module {
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
   } .elsewhen (io.boot) {
-    pc := UInt.Lit(0)
+    pc := UInt(0)
   } .otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index d827c096..392c4803 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -32,9 +32,9 @@ class SIntOps extends Module {
   io.subout := a -% b
   // TODO:
   //io.timesout := (a * b)(15, 0)
-  //io.divout := a / Mux(b === SInt.Lit(0), SInt.Lit(1), b)
+  //io.divout := a / Mux(b === SInt(0), SInt(1), b)
   //io.divout := (a / b)(15, 0)
-  //io.modout := SInt.Lit(0)
+  //io.modout := SInt(0)
   //io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
   io.rshiftout := (a >> 8) // (a >> ub).toSInt
   io.lessout := a < b
@@ -44,7 +44,7 @@ class SIntOps extends Module {
   io.lesseqout := a <= b
   io.greateqout := a >= b
   // io.negout := -a(15, 0).toSInt
-  io.negout := (SInt.Lit(0) -% a)
+  io.negout := (SInt(0) -% a)
 }
 
 /*
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 0c84e62a..a72af928 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module {
   val out       = Reg(init = UInt(0, width = 32))
 
   when (io.en) {
-    when(io.push && (sp < UInt.Lit(depth))) {
+    when(io.push && (sp < UInt(depth))) {
       stack_mem(sp) := io.dataIn
-      sp := sp +% UInt.Lit(1)
-    } .elsewhen(io.pop && (sp > UInt.Lit(0))) {
-      sp := sp -% UInt.Lit(1)
+      sp := sp +% UInt(1)
+    } .elsewhen(io.pop && (sp > UInt(0))) {
+      sp := sp -% UInt(1)
     }
-    when (sp > UInt.Lit(0)) {
-      out := stack_mem(sp -% UInt.Lit(1))
+    when (sp > UInt(0)) {
+      out := stack_mem(sp -% UInt(1))
     }
   }
   io.dataOut := out
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 40730264..66a06435 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -30,15 +30,15 @@ class Tbl(w: Int, n: Int) extends Module {
 class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), idxs.size)
   val dut = Module(new Tbl(w, n))
-  val vvalues = Vec(values.map(UInt.Lit(_)))
-  val vidxs = Vec(idxs.map(UInt.Lit(_)))
-  val prev_idx = vidxs(cnt - UInt.Lit(1))
-  val prev_value = vvalues(cnt - UInt.Lit(1))
+  val vvalues = Vec(values.map(UInt(_)))
+  val vidxs = Vec(idxs.map(UInt(_)))
+  val prev_idx = vidxs(cnt - UInt(1))
+  val prev_value = vvalues(cnt - UInt(1))
   dut.io.wi := vidxs(cnt)
   dut.io.ri := prev_idx
   dut.io.we := Bool(true) //TODO enSequence
   dut.io.d := vvalues(cnt)
-  when (cnt > UInt.Lit(0)) {
+  when (cnt > UInt(0)) {
     when (prev_idx === vidxs(cnt)) {
       assert(dut.io.o === vvalues(cnt))
     } .otherwise {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index b0f3a981..23eed15f 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -24,13 +24,13 @@ class FinishTester extends BasicTester {
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-  assert(test_wire === UInt.Lit(test_wire_override_value))
+  assert(test_wire === UInt(test_wire_override_value))
 
   /** In finish we use last connect semantics to alter the test_wire in the circuit
     * with a new value
     */
   override def finish(): Unit = {
-    test_wire := UInt.Lit(test_wire_override_value)
+    test_wire := UInt(test_wire_override_value)
   }
 }
 
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 69633461..ad5aecd8 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -31,10 +31,10 @@ class UIntOps extends Module {
   io.addout := a +% b
   io.subout := a -% b
   io.timesout := (a * b)(15, 0)
-  io.divout := a / Mux(b === UInt.Lit(0), UInt.Lit(1), b)
+  io.divout := a / Mux(b === UInt(0), UInt(1), b)
   // io.modout := a % b
   // TODO:
-  io.modout := UInt.Lit(0)
+  io.modout := UInt(0)
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
   io.lessout := a < b
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 22b518a2..e8bd66bd 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -12,15 +12,15 @@ import chisel3.util._
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
-    assert(a === UInt.Lit(b))
+    assert(a === UInt(b))
   }
   stop()
 }
 
 class TabulateTester(n: Int) extends BasicTester {
-  val v = Vec(Range(0, n).map(i => UInt.Lit(i * 2)))
-  val x = Vec(Array.tabulate(n){ i => UInt.Lit(i * 2) })
-  val u = Vec.tabulate(n)(i => UInt.Lit(i*2))
+  val v = Vec(Range(0, n).map(i => UInt(i * 2)))
+  val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
+  val u = Vec.tabulate(n)(i => UInt(i*2))
 
   assert(v.toBits === x.toBits)
   assert(v.toBits === u.toBits)
@@ -34,8 +34,8 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
-  when (cnt >= UInt.Lit(n)) {
-    val expected = cnt - UInt.Lit(n)
+  when (cnt >= UInt(n)) {
+    val expected = cnt - UInt(n)
     assert(shifter(0) === expected)
   }
   when (wrap) {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 2f5c49e4..07ab3444 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -13,19 +13,19 @@ class WhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt.width(3))
-  when(cnt.value === UInt.Lit(0)) {
-    out := UInt.Lit(1)
-  } .elsewhen (cnt.value === UInt.Lit(1)) {
-    out := UInt.Lit(2)
-  } .elsewhen (cnt.value === UInt.Lit(2)) {
-    out := UInt.Lit(3)
+  when(cnt.value === UInt(0)) {
+    out := UInt(1)
+  } .elsewhen (cnt.value === UInt(1)) {
+    out := UInt(2)
+  } .elsewhen (cnt.value === UInt(2)) {
+    out := UInt(3)
   } .otherwise {
-    out := UInt.Lit(0)
+    out := UInt(0)
   }
 
-  assert(out === cnt.value + UInt.Lit(1))
+  assert(out === cnt.value + UInt(1))
 
-  when(cnt.value === UInt.Lit(3)) {
+  when(cnt.value === UInt(3)) {
     stop()
   }
 }
@@ -35,19 +35,19 @@ class OverlappedWhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt.width(3))
-  when(cnt.value <= UInt.Lit(0)) {
-    out := UInt.Lit(1)
-  } .elsewhen (cnt.value <= UInt.Lit(1)) {
-    out := UInt.Lit(2)
-  } .elsewhen (cnt.value <= UInt.Lit(2)) {
-    out := UInt.Lit(3)
+  when(cnt.value <= UInt(0)) {
+    out := UInt(1)
+  } .elsewhen (cnt.value <= UInt(1)) {
+    out := UInt(2)
+  } .elsewhen (cnt.value <= UInt(2)) {
+    out := UInt(3)
   } .otherwise {
-    out := UInt.Lit(0)
+    out := UInt(0)
   }
 
-  assert(out === cnt.value + UInt.Lit(1))
+  assert(out === cnt.value + UInt(1))
 
-  when(cnt.value === UInt.Lit(3)) {
+  when(cnt.value === UInt(3)) {
     stop()
   }
 }