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-rw-r--r--src/test/scala/chiselTests/Stack.scala12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 0c84e62a..a72af928 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module {
val out = Reg(init = UInt(0, width = 32))
when (io.en) {
- when(io.push && (sp < UInt.Lit(depth))) {
+ when(io.push && (sp < UInt(depth))) {
stack_mem(sp) := io.dataIn
- sp := sp +% UInt.Lit(1)
- } .elsewhen(io.pop && (sp > UInt.Lit(0))) {
- sp := sp -% UInt.Lit(1)
+ sp := sp +% UInt(1)
+ } .elsewhen(io.pop && (sp > UInt(0))) {
+ sp := sp -% UInt(1)
}
- when (sp > UInt.Lit(0)) {
- out := stack_mem(sp -% UInt.Lit(1))
+ when (sp > UInt(0)) {
+ out := stack_mem(sp -% UInt(1))
}
}
io.dataOut := out