diff options
| author | Jim Lawson | 2016-07-25 14:06:51 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-25 17:07:33 -0700 |
| commit | 7aa05590382b0528799ad5e9f1318ce42e409793 (patch) | |
| tree | 9af7c7513f60efa30c59172a234a8f2926b5430f /src/test/scala/chiselTests/Stack.scala | |
| parent | 3624751e2e63ba9f107c795529edfe48cf8340b2 (diff) | |
Minimize differences with master.
Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Stack.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 0c84e62a..a72af928 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module { val out = Reg(init = UInt(0, width = 32)) when (io.en) { - when(io.push && (sp < UInt.Lit(depth))) { + when(io.push && (sp < UInt(depth))) { stack_mem(sp) := io.dataIn - sp := sp +% UInt.Lit(1) - } .elsewhen(io.pop && (sp > UInt.Lit(0))) { - sp := sp -% UInt.Lit(1) + sp := sp +% UInt(1) + } .elsewhen(io.pop && (sp > UInt(0))) { + sp := sp -% UInt(1) } - when (sp > UInt.Lit(0)) { - out := stack_mem(sp -% UInt.Lit(1)) + when (sp > UInt(0)) { + out := stack_mem(sp -% UInt(1)) } } io.dataOut := out |