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Diffstat (limited to 'src/test/scala/chiselTests/Reg.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Reg.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 8b9016b1..b66d7cb4 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20)) + val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt(20)) reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } |