diff options
| author | Jim Lawson | 2016-07-25 14:06:51 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-25 17:07:33 -0700 |
| commit | 7aa05590382b0528799ad5e9f1318ce42e409793 (patch) | |
| tree | 9af7c7513f60efa30c59172a234a8f2926b5430f /src/test/scala/chiselTests/Reg.scala | |
| parent | 3624751e2e63ba9f107c795529edfe48cf8340b2 (diff) | |
Minimize differences with master.
Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.
Diffstat (limited to 'src/test/scala/chiselTests/Reg.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Reg.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 8b9016b1..b66d7cb4 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20)) + val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt(20)) reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } |