Introduce chiselCloneType to distinguish from cloneType.

Still fails one test - DirectionSpec in Direction.scala

5 files changed, 9 insertions, 15 deletions

diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 037f9a22..76bf4842 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -12,7 +12,7 @@ class DecoupledIO[+T <: Data](gen: T) extends Bundle
 {
   val ready = Input(Bool())
   val valid = Output(Bool())
-  val bits  = Output(gen.cloneType)
+  val bits  = Output(gen.chiselCloneType)
   override def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
 }
 
@@ -59,9 +59,7 @@ object DecoupledIO {
     }
   }
 //  override def cloneType: this.type = {
-//    val clone = DeqIO(gen).asInstanceOf[this.type]
-//    clone.unBind()
-//    clone
+//    DeqIO(gen).asInstanceOf[this.type]
 //  }
 }
 
@@ -171,7 +169,7 @@ extends Module(override_reset=override_reset) {
 object Queue
 {
   def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T]  = {
-    val q = Module(new Queue(enq.bits.cloneType, entries, pipe))
+    val q = Module(new Queue(enq.bits.chiselCloneType, entries, pipe))
     q.io.enq.valid := enq.valid // not using <> so that override is allowed
     q.io.enq.bits := enq.bits
     enq.ready := q.io.enq.ready
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 81de4754..f77a9667 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -26,12 +26,12 @@ object RegEnable
 {
   def apply[T <: Data](updateData: T, enable: Bool): T = {
     val r = Reg(updateData)
-    when (enable) { r := updateData }
+    when (enable) { r := updateData.chiselCloneType }
     r
   }
   def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
     val r = RegInit(resetData)
-    when (enable) { r := updateData }
+    when (enable) { r := updateData.chiselCloneType }
     r
   }
 }
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 5641f0f2..743038f3 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -11,13 +11,9 @@ import chisel3._
 class Valid[+T <: Data](gen: T) extends Bundle
 {
   val valid = Output(Bool())
-  val bits  = Output(gen.cloneType)
+  val bits  = Output(gen.chiselCloneType)
   def fire(dummy: Int = 0): Bool = valid
-  override def cloneType: this.type = {
-    val clone = Valid(gen).asInstanceOf[this.type]
-    clone.unBind()
-    clone
-  }
+  override def cloneType: this.type = Valid(gen).asInstanceOf[this.type]
 }
 
 /** Adds a valid protocol to any interface */
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index c5aaa554..fce2c602 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
-    new Complex(re.cloneType, im.cloneType).asInstanceOf[this.type]
+    new Complex(re.chiselCloneType, im.chiselCloneType).asInstanceOf[this.type]
 }
 
 class ComplexAssign(w: Int) extends Module {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 59451a2b..26953f5f 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
 
 class ModuleWire extends Module {
   val io = IO(new SimpleIO)
-  val inc = Wire(Module(new PlusOne).io.cloneType)
+  val inc = Wire(Module(new PlusOne).io.chiselCloneType)
   inc.in := io.in
   io.out := inc.out
 }