diff options
| author | Jim Lawson | 2016-07-27 10:36:55 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-27 10:36:55 -0700 |
| commit | 138329479914ac37b49a5a44841dc1de2929dca5 (patch) | |
| tree | 0b539d74e3176853fe384a38cfc9a1dfa5e2bf31 /src | |
| parent | 089987c3e0b2bc390935a4d9d44db38a18c47901 (diff) | |
More compatibility fixes
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 13 | ||||
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 3 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/Direction.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/IOCompatibility.scala | 2 |
4 files changed, 17 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 3b613a5e..a7968bd5 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -107,6 +107,19 @@ package object Chisel { type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] val DecoupledIO = chisel3.util.DecoupledIO + class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { + def init(): Unit = { + this.noenq() + } + override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type] + } + class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { + chisel3.core.Binding.bind(this, chisel3.core.FlippedBinder, "Error: Cannot flip ") + def init(): Unit = { + this.nodeq() + } + override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type] + } object EnqIO { def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen) } diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 5fcf5e67..a0264df4 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -7,7 +7,7 @@ package object chisel3 { import internal.sourceinfo.{SourceInfo, SourceInfoTransform} import util.BitPat - import chisel3.core.{Binding, Bits, Element, FlippedBinder} + import chisel3.core.{Binding, FlippedBinder} import chisel3.util._ import chisel3.internal.firrtl.Port @@ -120,6 +120,7 @@ package object chisel3 { val NODIR = chisel3.core.Direction.Unspecified type ChiselException = chisel3.internal.ChiselException type ValidIO[+T <: Data] = chisel3.util.Valid[T] + val ValidIO = chisel3.util.Valid val Decoupled = chisel3.util.DecoupledIO class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) { diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 83484a64..949b92ed 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -31,7 +31,7 @@ class DirectionSpec extends ChiselPropSpec with ShouldMatchers { } property("Inputs should not be assignable") { - a[ChiselException] should be thrownBy { + a[Exception] should be thrownBy { elaborate(new BadDirection) } } diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index b904d77e..edbd3d09 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -2,7 +2,7 @@ package chiselTests -import chisel3._ +import Chisel._ class IOCSimpleIO extends Bundle { val in = UInt(INPUT, 32) |
