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authorJim Lawson2016-08-30 08:50:52 -0700
committerJim Lawson2016-08-30 08:50:52 -0700
commit98e35eb6b46b144e3daec78e21e807769e6db505 (patch)
tree686110063b9c719e3d84f22961b83fa702c77dc2 /src
parentd4375d8c7a380d8002b7d9e79f53883e46279cd9 (diff)
Allow compileOptions as optional arguments to elaborate() and emit().
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/chisel3/Driver.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 20a43636..8efb529d 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -108,9 +108,9 @@ object Driver extends BackendCompilationUtilities {
* @param gen a function that creates a Module hierarchy
* @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR)
*/
- def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen()))
+ def elaborate[T <: Module](gen: () => T, moduleCompileOptions: Option[ExplicitCompileOptions] = None): Circuit = Builder.build(Module(gen()), moduleCompileOptions)
- def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen))
+ def emit[T <: Module](gen: () => T, moduleCompileOptions: Option[ExplicitCompileOptions] = None): String = Emitter.emit(elaborate(gen, moduleCompileOptions))
def dumpFirrtl(ir: Circuit, optName: Option[File]): File = {
val f = optName.getOrElse(new File(ir.name + ".fir"))